Datasheet

Data Sheet ADF4158
Rev. E | Page 33 of 36
SPUR MECHANISMS
The fractional interpolator in the ADF4158 is a third-order Σ-Δ
modulator (SDM) with a 25-bit fixed modulus (MOD). The SDM
is clocked at the PFD reference rate (f
PFD
) that allows PLL output
frequencies to be synthesized at a channel step resolution of f
PFD
/
MOD. The various spur mechanisms possible with fractional-N
synthesizers and how they affect the ADF4158 are discussed in
this section.
Fractional Spurs
In most fractional synthesizers, fractional spurs can appear at
the set channel spacing of the synthesizer. In the ADF4158,
these spurs do not appear. The high value of the fixed modulus
in the ADF4158 makes the SDM quantization error spectrum
look like broadband noise, effectively spreading the fractional
spurs into noise.
Integer Boundary Spurs
Interactions between the RF VCO frequency and the PFD
frequency can lead to spurs known as integer boundary spurs.
When these frequencies are not integer related (which is the
purpose of the fractional-N synthesizer), spur sidebands appear on
the VCO output spectrum at an offset frequency that corresponds
to the beat note or difference frequency between an integer
multiple of the PFD and the VCO frequency.
These spurs are named integer boundary spurs because they are
more noticeable on channels close to integer multiples of the PFD
where the difference frequency can be inside the loop bandwidth.
These spurs are attenuated by the loop filter on channels far
from integer multiples of the PFD.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism that
bypasses the loop can cause a problem. One such mechanism is
the feedthrough of low levels of on-chip reference switching noise
out through the RF
IN
pins back to the VCO, resulting in reference
spur levels as high as −90 dBc. Take care in the PCB layout to
ensure that the VCO is well separated from the input reference
to avoid a possible feedthrough path on the board.
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum; however,
RF frequencies lower than this can be used if the minimum slew
rate specification of 400 V/µs is met. An appropriate LVDS driver
can be used to square up the RF signal before it is fed back to the
ADF4158 RF input. The FIN1001 from Fairchild Semiconductor
is one such LVDS driver.
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help the user
implement PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLL™ software. This software designs,
simulates, and analyzes the entire PLL frequency domain and time
domain response. Various passive and active filter architectures
are allowed.
PCB DESIGN GUIDELINES FOR THE CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-24) are rectangular.
The printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. Center the land on the pad. This ensures
that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
should be incorporated into the thermal pad at 1.2 mm pitch
grid. The via diameter should be between 0.3 mm and 0.33 mm,
and the via barrel should be plated with 1 ounce of copper to
plug the via. Connect the PCB thermal pad to AGND.