Datasheet

Data Sheet ADF4158
Rev. E | Page 31 of 36
Note that DB[22:21] in Register R4 should be set to 2 and
DB[30:27] in Register R0 (MUXOUT control) should be
set to 15 (1111).
The mechanism of how single bits are read back is shown in
Figure 43.
For continuous frequency readback the following sequence
should be used:

Register 0 write

LE high

Pulse on TX
DATA

Frequency readback (as described at the beginning of the
Interrupt Modes and Frequency Readback section and
Figure 43)

Pulse on TX
DATA

Register R4 write

Frequency readback (as described at the beginning of the
Interrupt Modes and Frequency Readback section and
Figure 43)

Pulse on TX
DATA

…
The sequence is also shown in Figure 44.
08728-101
MUXOUT
CLK
LE
TX
DATA
DAT
A
CLOCKED OUT ON POSITIVE EDGE OF CLK
A
ND READ ON NE
G
A
TIVE EDGE
OF CLK READBACK WORD (37 BITS)
0 0001 1100 1111 0110 0010 0011 1010 0111 1000 (HEX 01CF623A78)
LSBMSB
12-BIT INTERGER WORD
0000 1110 0111
0x0E7
231
25-BIT FRAC WORD
1 0110 0010 0011 1010 0111 1000
0x1623A78
23214712
RF = F
PFD
× (231 + 23214712 ÷ 2
25
) = 5.7922963GHz
Figure 43. Reading Back Single Bits to Determine the Output Frequency at the Moment of Interrupt
CLK
MUXOUT
LE
TX
DATA
DATA
R0 WRITE R4 WRITE R4 WRITE
FREQUENCY
READBACK
FREQUENCY
READBACK
FREQUENCY
READBACK
37 CLK
PULSES
37 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
32 CLK
PULSES
32 CLK
PULSES
0
8728-144
Figure 44. Continuous Frequency Readback