Datasheet

Data Sheet ADF4158
Rev. E | Page 21 of 36
TEST REGISTER (R4) MAP
With Register R4 DB[2:0] set to [1, 0, 0], the on-chip test
register (R4) is programmed as shown in Figure 27.
LE SEL
In some applications, it is necessary to synchronize LE with
the reference signal. To do this, DB31 should be set to 1.
Synchronization is done internally on the part.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
Negative Bleed Current
Setting Bits DB[24:23] to 11 turns on the constant negative
bleed current. This ensures that the charge pump operates out
of the dead zone. Thus, the phase noise is not degraded and the
level of spurs is lower. Enabling constant negative bleed current
is particularly important on channels close to multiple PFD
frequencies. Refer to the AN-1154 Application Note for more
information on the negative bleed current. When using negative
bleed current, readback to MUXOUT must be disabled.
Readback to MUXOUT
DB[22:21] enable or disable the readback to MUXOUT function.
This function allows reading back the synthesizer’s frequency at
the moment of interrupt. When using readback to MUXOUT,
negative bleed current must be off.
CLK DIV Mode
Depending on the settings of DB[20:19], the 12-bit clock divider
may be a counter for the switched R fast-lock ramp (CLK2), or
it may be turned off.
12-Bit Clock Divider Value
DB[18:7] program the clock divider, which is used as a timer for
ramp − CLK
2
, while operating in ramp mode. See the Wavefor m
Deviations and Timing section for more details. The timer also
determines how long the loop remains in wideband mode while
the switched R fast-lock technique is used. See Fast-Lock Timer
and Register Sequences for more details.
DB31
12-BIT CLOCK DIVIDER VALUERESERVED
LE SEL
RESERVED
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26
DB25 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14
DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2 DB1 DB0
LS1 0 0 0 0 0 0 R2
R1 CK2 CK1 D12 D11 D10 D9 D8 D7 D6 D5 D4
D3 D2 D1 C3(1) C2(0) C1(0)
LS1 LE SEL
0 LE FROM PIN
1 LE SYNC WITH REF
D12 D11 .......... D2 D1
CLOCK DIVIDER VALUE
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
0
1
2
3
.
.
.
4092
4093
4094
4095
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
CK2 CK1
CLOCK DIVIDER MODE
0 0
CLOCK DIVIDER OFF
0 1
FAST-LOCK DIVIDER
1 0
RESERVED
1 1 RAMP DIVIDER
0 0
0
0
CLK
DIV
MODE
READ-
BACK
TO
MUXOUT
08728-115
DB24 DB23
NB2 NB1
NEG
BLEED
CURR-
ENT
R2 READBACK TO MUXOUT
0 DISABLED
1
ENABLED
R1
0
0
NB2 NEGATIVE BLEED CURRENT
0 OFF
1
ON
NB1
0
1
Figure 27. Test Register (R4) Map