Datasheet

ADF4158 Data Sheet
Rev. E | Page 12 of 36
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 19 shows a simplified schematic
of the PFD. The PFD includes a fixed delay element that sets the
width of the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
U3
CLR2
Q2D2
U2
DOWN
U
P
HIGH
HIGH
C
P
–IN
+IN
CHARGE
PUM
P
DEL
AY
CLR1
Q1
D1
U1
08728-017
Figure 19. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4158 allows the user to access
various internal points on the chip. The state of MUXOUT is
controlled by the M4, M3, M2, and M1 bits (see Figure 23).
Figure 20 shows the MUXOUT section in block diagram form.
MUXOUT
DV
DD
THREE-STATE OUTPUT
N-DIVIDER OUTPUT
DV
DD
DGND
DGND
R-DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
R-DIVIDER/2
N-DIVIDER/2
FAST-LOCK SWITCH
READBACK TO MUXOUT
CONTROLMUX
08728-009
Figure 20. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4158 digital section includes a 5-bit RF R-counter, a
12-bit RF N-counter, and a 25-bit FRAC counter. Data is clocked
into the 32-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of eight latches on the rising edge of LE. The
destination latch is determined by the state of the three control
bits (C3, C2, and C1) in the shift register. These are the three
LSBs—DB2, DB1, and DB0—as shown in Figure 2. The truth
table for these bits is shown in Table 6. Figure 21 and Figure 22
show a summary of how the latches are programmed.
PROGRAM MODES
Table 6 and Figure 23 through Figure 30 show how to set up the
program modes in the ADF4158.
Several settings in the ADF4158 are double buffered. These include
the LSB fractional value, R-counter value, reference doubler,
current setting, and RDIV2. This means that two events must
occur before the part uses a new value for any of the double-
buffered settings. First, the new value is latched into the device
by writing to the appropriate register. Second, a new write must
be performed on Register R0.
For example, updating the fractional value can involve a write to
the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should be
written to first, followed by the write to R0. The frequency change
begins after the write to R0. Double buffering ensures that the
bits written to in R1 do not take effect until after the write to R0.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3 C2 C1 Register
0 0 0 R0
0 0 1 R1
0 1 0 R2
0 1 1 R3
1 0 0 R4
1 0 1 R5
1 1 0 R6
1 1 1 R7