Datasheet

Data Sheet ADF4158
Rev. E | Page 11 of 36
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
BUFFER
TO R-COUNTER
REF
IN
100k
Ω
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
08728-027
Figure 16. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 17. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AV
DD
2kΩ 2kΩ
RF
IN
B
RF
IN
A
08728-015
Figure 17. RF Input Stage
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 23 to 4095 are allowed.
25-BIT FIXED MODULUS
The ADF4158 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of
f
RES
= f
PFD
/2
25
(1)
where f
PFD
is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible.
INT, FRAC, AND R RELATIONSHIP
The INT and FRAC values, in conjunction with the R-counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). The RF VCO
frequency (RF
OUT
) equation is
RF
OUT
= f
PFD
× (INT + (FRAC/2
25
)) (2)
where:
RF
OUT
is the output frequency of external voltage controlled
oscillator (VCO).
INT is the preset divide ratio of binary 12-bit counter (23 to 4095).
FRAC is the numerator of the fractional division (0 to 2
25
− 1).
f
PFD
= REF
IN
× [(1 + D)/(R × (1 + T))] (3)
where:
REF
IN
is the reference input frequency.
D is the REF
IN
doubler bit (0 or 1).
T is the REF
IN
divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
THIRD-ORDER
FRACTIONAL
INTERPOLAT
OR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVIDER N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
08728-016
Figure 18. RF N-Divider
R-COUNTER
The 5-bit R-counter allows the input reference frequency (REF
IN
)
to be divided down to produce the reference clock to the PFD.
Division ratios from 1 to 32 are allowed.