Datasheet

Data Sheet ADF4157
Rev. D | Page 9 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
open. This ensures that there is no loading of the REF
IN
pin on
power-down.
BUFFER
TO R COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NC
NC
SW1
POWER-DOWN
CONTROL
05874-005
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by
a two-stage limiting amplifier to generate the current mode
logic (CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AV
DD
2kΩ 2kΩ
RF
IN
B
RF
IN
A
05874-006
Figure 12. RF Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
25-BIT FIXED MODULUS
The ADF4157 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of
f
RES
= f
PFD
/2
25
where f
PFD
is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible.
INT, FRAC, AND R RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the RF
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RF
OUT
) equation is
RF
OUT
= f
PFD
× (INT + (FRAC/2
25
)) (1)
where:
RF
OUT
is the output frequency of the external voltage controlled
oscillator (VCO).
INT is the preset divide ratio of the binary 12-bit counter (23 to
4095).
FRAC is the numerator of the fractional division (0 to 2
25
− 1).
f
PFD
= REF
IN
× [(1 + D)/(R × (1 + T))] (2)
where:
REF
IN
is the reference input frequency.
D is the REF
IN
doubler bit.
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
T is the REF
IN
divide-by-2 bit (0 or 1).
RF R COUNTER
The 5-bit RF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 32 are allowed.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N DIVIDER N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
05874-007
Figure 13. RF N Divider