Datasheet

Data Sheet ADF4157
Rev. D | Page 3 of 24
SPECIFICATIONS
AV
DD
= DV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter
B Version
1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Frequency (RF
IN
)
0.5/6.0
GHz min/max
−10 dBm/0 dBm min/max; for lower frequencies, ensure slew rate
(SR) > 400 V/µs
REFERENCE CHARACTERISTICS
REF
IN
Input Frequency 10/300 MHz min/max For f
REFIN
< 10 MHz, ensure slew rate > 50 V/µs
REF
IN
Input Sensitivity
0.4/AV
DD
V p-p min/max
For 10 MHz < f
REFIN
< 250 MHz, biased at AV
DD
/2
2
0.7/AV
DD
V p-p min/max
For 250 MHz < f
REFIN
< 300 MHz, biased at AV
DD
/2
2
REF
IN
Input Capacitance
10
pF max
REF
IN
Input Current
±100
µA max
PHASE DETECTOR
Phase Detector Frequency
3
32
MHz max
CHARGE PUMP
I
CP
Sink/Source
Programmable
High Value 5 mA typ With R
SET
= 5.1 kΩ
Low Value
312.5
µA typ
Absolute Accuracy 2.5 % typ With R
SET
= 5.1 kΩ
R
SET
Range
2.7/10
kΩ min/max
I
CP
Three-State Leakage Current
1
nA typ
Sink and source current
Matching 2 % typ 0.5 V < V
CP
< V
P
– 0.5
I
CP
vs. V
CP
2
% typ
0.5 V < V
CP
< V
P
– 0.5
I
CP
vs. Temperature
2
% typ
V
CP
= V
P
/2
LOGIC INPUTS
V
INH
, Input High Voltage 1.4 V min
V
INL
, Input Low Voltage
0.6
V max
I
INH
/I
INL
, Input Current ±1 µA max
C
IN
, Input Capacitance
10
pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage
1.4
V min
Open-drain 1 kΩ pull-up to 1.8 V
V
OH
, Output High Voltage VDD – 0.4 V min CMOS output chosen
V
OL
, Output Low Voltage
0.4
V max
I
OL
= 500 µA
POWER SUPPLIES
AV
DD
2.7/3.3
V min/max
DV
DD
AV
DD
V
P
AV
DD
/5.5
V min/V max
I
DD
29
mA max
23 mA typical
Low Power Sleep Mode 10 µA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PN
SYNTH
)
4
−211
dBc/Hz typ
PLL loop B/W = 500 kHz;
measured at 100 kHz
Normalized 1/f Noise (PN
1_f
)
5
−110
dBc/Hz typ
10 kHz offset; normalized to 1 GHz
Phase Noise Floor
6
−137 dBc/Hz typ @ 10 MHz PFD frequency
−133
dBc/Hz typ
@ 25 MHz PFD frequency
Phase Noise Performance
7
@ VCO output
5800 MHz Output
8
−87 dBc/Hz typ @ 2 kHz offset, 25 MHz PFD frequency
1
Operating temperature of B version is −40°C to +85°C.
2
AC-coupling ensures AV
DD
/2 bias.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(F
PFD
). PN
SYNTH
= PN
TOT
− 10 log(F
PFD
) − 20 log(N).
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, F
RF
,
and at a frequency offset f is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(F
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
7
The phase noise is measured with the EV-ADF4157SD1Z and the Agilent E5052A phase noise system.
8
f
REFIN
= 100 MHz; f
PFD
= 25 MHz; offset frequency = 2 kHz; RF
OUT
= 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.