Datasheet

Data Sheet ADF4157
Rev. D | Page 17 of 24
TEST REGISTER (R4) MAP
With R4[2:0] set to 100, the on-chip test register (R4) is
programmed as shown in Figure 21.
Negative Bleed Current
Setting Bits DB[24:23] to 11 turns on the constant negative
bleed current. This ensures that the charge pump operates out
of the dead zone. Thus the phase noise is not degraded and the
level of spurs is lower. Enabling constant negative bleed current
is particularly important on channels close to multiple PFD
frequencies.
CLK Divider Mode
Setting Bits DB[20:19] to 01 enables switched R fastlock.
12-Bit Clock Divider Value
Bits DB[18:7] are used to program the clock divider, which
determines for how long the loop remains in wideband mode
while the switched R fastlock technique is used.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
DB31
12-BIT CLOCK DIVIDER VALUERESERVED RESERVED
RESERVED
CONTROL
BITS
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 NB2 NB1 0 0 C2 C1 D12 D11 D1
0 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)
05874-015
NB2 NB1 NEGATIVE BLEED CURRENT
0 0 OFF
1 1 ON
D12 D11 .......... D2 D1 CLOCK DIVIDER VALUE
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095
C2 C1 CLOCK DIVIDER MODE
0 0
CLOCK DIVIDER OFF
0 1 SWITCHED R FASTLOCK ENABLE
0 0
0
0
NEG
BLEED
CURR-
ENT
CLK
DIV
MODE
Figure 21. Test Register (R4) Map