Datasheet

ADF4156 Data Sheet
Rev. E | Page 8 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. While the
device is operating, SW1 and SW2 are usually closed switches
and SW3 is open. When a power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that the
REF
IN
pin is not loaded while the device is powered down.
BUFFER
TO R-COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
05863-005
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
two-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
BI
AS
G
EN
ERA
T
OR
1.6
V
AG
ND
A
V
D
D
RF
IN
B
RF
IN
A
2kΩ
2k
Ω
05863-006
Figure 12. RF Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R-counter, enable generating output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the RF
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RF
OUT
) equation is
RF
OUT
= F
PFD
× (INT + (FRAC/MOD)) (1)
where RF
OUT
is the output frequency of an external voltage-
controlled oscillator (VCO).
F
PFD
= REF
IN
× [(1 + D)/(R × (1 + T))] (2)
where:
REF
IN
is the reference input frequency.
D is the REF
IN
doubler bit.
T is the REF
IN
divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVIDER N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
05863-007
Figure 13. RF INT Divider
RF R-COUNTER
The 5-bit RF R-counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 32 are allowed.