Datasheet

ADF4156 Data Sheet
Rev. E | Page 20 of 24
PHASE RESYNC
The output of a fractional-N PLL can settle to any MOD phase
offset with respect to the input reference, where MOD is the
fractional modulus. The phase resync feature in the ADF4156 is
used to produce a consistent output phase offset with respect to
the input reference. This is necessary in applications where the
output phase and frequency are important, such as digital beam
forming. See the Phase Programmability section for information
about how to program a specific RF output phase when using
the phase resync feature.
Phase resync is enabled by setting Bits DB[20:19] in Register R4
to 10. When phase resync is enabled, an internal timer generates
sync signals at intervals of t
SYNC
as indicated by the following
formula:
t
SYNC
= CLK_DIV_VALUE × MOD × t
PFD
where:
t
PFD
is the PFD reference period.
CLK_DIV_VALUE is the decimal value programmed in
Bit DB[18:7] of Register R4. This value can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bit DB[14:3] of
Register R2.
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The t
SYNC
time should be programmed to
a value that is at least as long as the worst-case lock time. Doing
so guarantees that the phase resync occurs after the last cycle
slip in the PLL settling transient.
In the example shown in Figure 24, the PFD reference is
25 MHz and the MOD value is 125 for a 200 kHz channel
spacing. Therefore, t
SYNC
is set to 400 µs by programming
CLK_DIV_VALUE to 80.
LE
PHASE
FREQUENCY
SYNC
(Internal)
–100
0
100
200 1000
300
400 500 600 700 800 900
05863-016
TIME (µs)
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
t
SYNC
LAST CYCLE SLIP
PLL SETTLES TO
INCORRECT PHASE
Figure 24. Phase Resync Example
Phase Programmability
To program a specific RF output phase, change the phase word
in Register R1. As this word is swept from 0 to MOD, the RF output
phase sweeps over a 360
o
/MOD range in steps of 360
o
/MOD.
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum; however,
lower RF frequencies can be used if the minimum slew rate
specification of 400 V/µs is met. An appropriate LVDS driver, such
as the FIN1001 from Fairchild Semiconductor, can be used to
square up the RF signal before it is fed back into the ADF4156
RF input.
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help implement
the PLL design. Visit www.analog.com/pll for a free download
of the ADIsimPLL™ software. This software designs, simulates,
and analyzes the entire PLL frequency domain and time domain
response. Various passive and active filter architectures are allowed.
When designing the loop filter, keep the ratio of the PFD frequency
to the loop bandwidth >200:1 to attenuate the Σ-Δ modulator noise.