Datasheet

ADF4156 Data Sheet
Rev. E | Page 16 of 24
CLK DIV REGISTER, R4
With the control bits (Bits[2:0]) of Register R3 set to 100, the
on-chip clock divider register (R4) is programmed. Figure 21
shows the input data format for programming this register.
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for
activation of the fast-lock mode or a phase resync. See the Phase
Resync section for more information.
Clock Divider Mode
DB[20:19] control the mode of the clock divider in the ADF4156.
These bits should be set to 01 to activate the fast-lock mode, or
to 10 to activate a phase resync. In most applications, neither a
fast lock nor a phase resync is required. In this case, DB[20:19]
should be set to 00.
RESERVED BITS
All reserved bits should be set to 0 for normal operation.
INITIALIZATION SEQUENCE
After powering up the part, the correct register programming
sequence is as follows:
1. CLK DIV register (R4)
2. Function register (R3)
3. MOD/R register (R2)
4. Phase register (R1)
5. FRAC/INT register (R0)
DB31
DB30 DB29 DB28 DB27 DB26 DB25 DB24
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0
M2 M1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 R4 R3 R2 R1 C3(1) C2(0)
C1(0)
CONTROL
BITS
RESERVEDRESERVED
CLK
DIV
MODE
12-BIT CLOCK
DIVIDER
VALUE
M2 M1
CLK DIV MODE
0 0 CLK DIV OFF
0 1 FAST-LOCK MODE
1 0 R
ESYNC TIMER ENABLED
1 1
RESERVED
D12 D11
.......... D2 D1 CLOCK DIVIDER VALUE
0 0 .......... 0 0 0
0 0 .......... 0 1
1
0 0 .......... 1
0 2
0
0 .......... 1
1 3
. . .......... .
. .
. . ..........
. . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1
.......... 0
1 4093
1 1 .......... 1 0 4094
1 1 ..........
1 1 4095
05863-015
Figure 21. CLK DIV Register (R4) Map