Datasheet

ADF4153 Data Sheet
Rev. F | Page 14 of 24
Table 9. Control Register Map (R2)
U3 POWER-DOWN
0 NORMA
L
OPERA
TION
1 POWER-DOWN
U4
LDP
0
1
24 PFD CYCLES
40 PFD CYCLES
I
CP
(mA)
CP3 CP2
CP1 CP0
2.7kΩ 5.1kΩ 10kΩ
0 1.18 0.63
0.32
0
2.46 1.25 0.64
0 3.54
1.88 0.96
0 4.72 2.50
1.28
0 5.9 3.13 1.59
0 7.08
3.75 1.92
0 8.26
4.38 2.23
0 9.45
5.00 2.55
1 0.59
0.31 0.16
1 1.23
0.63 0.32
1 1.77
0.94 0.48
1 2.36 1.25
0.64
1 2.95 1.57
0.8
1
3.54 1.88
0.96
1 4.13 2.19
1.12
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 4.73 2.50 1.28
U5 PD POLARITY
0 NEG
ATIVE
1 POSITIVE
U2
CP
THREE-STA
TE
0
DISABLED
1 THREE-S
TATE
U1
COUNTER RESET
0 DISABLED
ENABLED
1
REFERENCE
DOUBLER
U6
0
DISABLED
1 ENABLED
REFERENCE
DOUBLER
DB14
DB13
DB12 DB
11
DB10
DB9 DB8
DB7 DB6
DB5
DB4 DB3
DB2
DB1 DB0
C2 (1)
C1 (0)
U1U2
U3U4
U5CP0
CP1CP2
U6
S1S2
S3
S4
CONTRO
L
BITS
CP
CURRENT
SETTING
PD POLARIT
Y
RESYNC
LD
P
POWER-
DOWN
C
P
THREE-STA
TE
COUNTER
RESET
DB15
CP3
CP/2
S4 S3 S2
S1 RESYNC
0
1
1
0
0 2
0 1
3
.
. .
. .
.
.
. .
1 1
13
1
0 14
1
0
0
0
.
.
.
1
1
1
0
1
1
.
.
.
0
1
1
1 15
03685-022