Datasheet

Data Sheet ADF4153
Rev. F | Page 13 of 24
Table 8. R Divider Register Map (R1)
M12
INTERPOL
ATOR
MODULUS
V
ALUE (MOD)
M
11
M10
M3 M2
M1
0 0
..........
0 1
0
2
0
0
.......... 0
1
1 3
0 0 .......... 1 0
0 4
. . .......... . . . .
. . ..........
. . . .
. . .......... . . . .
1 1 .......... 1 0 0 4092
1 1 .......... 1 0 1 4093
1 1
.......... 1 1 0 4094
1
0
0
0
.
.
.
1
1
1
1 1 .......... 1 1 1 4095
RF R COUNTER
DIVIDE RATIO
R4 R3 R2 R1
0
0
0
0
.
.
.
1 12
1 13
1 14
1
0
0
0
1
.
.
.
1
1
1
1
0
1
1
0
.
.
.
0
0
1
1
1
0
1
0
.
.
.
1
2
3
4
.
.
.
0
1
0
1
15
P1
PRESCALER
0
4/5
1
8/9
DB18 DB17 DB16
DB15 DB14
DB13
DB12 DB
11 DB10 DB9 DB8 DB7 DB6 DB5
DB4 DB3
DB2
DB1 DB0
C2 (0) C1 (1)
M1M2M3M4M5M6M7
M8
M9M10
M1
1
M12R1R3R4
CONTROL
BITS
12-BIT INTERPOLA
TOR MODULUS VALUE (MOD)
4-BIT R COUNTER
R2
MUXOUT
0
DB20 DB19
P1M1
DB23
DB22 DB21
M2M3
P3
LOAD
CONTROL
RESE
RVED
PRESCALER
P3
LOAD CONTROL
0 NORMA
L
OPERA
TION
1 LOAD RESYNC
M3 M2 M1 MUXOUT
0 THREE-STA TE OUTPUT
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
0
0 N DIVIDER OUTPUT
LOGIC HIGH
LOGIC LOW
0
1 R DIVIDER OUTPUT
1
1 FASTLOCK SWITCH
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
03685-021