Datasheet

Data Sheet ADF4153A
Rev. A | Page 13 of 24
U3 POWER-DOWN
0 NORMAL OPERATION
1 POWER-DOWN
U4 LDP
0
1
24 PFD CYCLES
40 PFD CYCLES
U5 PD POLARITY
0 NEGATIVE
1 POSITIVE
U2 CP THREE-STATE
0 DISABLED
1 THREE-STATE
U1 COUNTER RESET
0 DISABLED
ENABLED1
REFERENCE
DOUBLER
U6
0 DISABLED
1 ENABLED
REFERENCE
DOUBLER
DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)
U1U2U3U4U5CP0CP1CP2U6S1S2S3S4
CONTROL
BITS
CP CURRENT
SETTING
PD POLARITY
RESYNC
LDP
POWER-
DOWN
CP
THREE-STATE
COUNTER
RESET
DB15
CP3
CP/2
S4 S3 S2 S1 RESYNC
0 1 1
0 0 2
0 1 3
. . .
. . .
. . .
1 1 13
1 0 14
1
0
0
0
.
.
.
1
1
1
0
1
1
.
.
.
0
1
1 1 15
I
CP
(mA)
CP3 CP2 CP1 CP0 3.0kΩ 4.7kΩ 10kΩ
0 0.979 0.625 0.294
0 1.958 1.250 0.588
0 2.938 1.875 0.881
0 3.917 2.500 1.175
0 4.896 3.125 1.469
0 5.875 3.750 1.763
0 6.854 4.375 2.056
0 7.833 5.000 2.350
1 0.490 0.313 0.147
1 0.979 0.625 0.294
1 1.469 0.938 0.441
1 1.958 1.250 0.588
1 2.448 1.563 0.734
1 2.938 1.875 0.881
1 3.427 2.188 1.028
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 3.917 2.500 1.175
11047-019
Figure 19. Control Register Map (R2)