Datasheet

ADF4153A Data Sheet
Rev. A | Page 10 of 24
REGISTER MAPS
NOISE AND SPUR REG (R3)
DB10
DB9 DB8 DB7 DB6
DB5 DB4 DB3 DB1 DB0
C2 (1)
C1 (1)
T100
0T5T6
T7T8
NOISE AND SPUR
MODE
DB2
0
NOISE
AND SPUR
MODE
RESERVED
N DIVIDER REG (R0)
DB20 DB19
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6
DB5 DB4
DB3 DB2
DB1 DB0
C2 (0)
C1 (0)F1
F2F3F4F5F6F7F8F9F10F11F12N1
N3N4
N5N6
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
12-BIT FRACTIONAL VALUE (FRAC)
DB23 DB22 DB21
N7N8N9
9-BIT INTEGER VALUE (INT)
N2
FASTLOCK
FL1
R DIVIDER REG (R1)
DB18
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3 DB2
DB1 DB0
C2 (0) C1 (1)
M1
M2
M3M4M5M6M7M8M9M10M11M12R1R3R4
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
4-BIT
R COUNTER
R2
MUXOUT
0
DB20
DB19
P1
M1
DB23 DB22 DB21
M2M3P3
LOAD
CONTROL
RESERVED
RESERVED
PRESCALER
CONTROL REG (R2)
REFERENCE
DOUBLER
DB14 DB13 DB12 DB11
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2 DB1 DB0
C2 (1) C1 (0)
U1U2
U3U4U5CP0CP1CP2U6
S1S2S3S4
CP CURRENT
SETTING
PD POLARITY
RESYNC
LDP
POWER-
DOWN
CP
THREE-STATE
COUNTER
RESET
DB15
CP3
CP/2
11047-016
Figure 16. Register Summary