Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Circuit Description
- Register Maps
- Register 0
- Register 1
- Register 2
- Register 3
- Register 4
- Initialization Sequence
- RF Synthesizer—A Worked Example
- Modulus
- Reference Doubler and Reference Divider
- 12-Bit Programmable Modulus
- Cycle Slip Reduction for Faster Lock Times
- Spurious Optimization and Fast lock
- Fast Lock Timer and Register Sequences
- Fast Lock—An Example
- Fast Lock—Loop Filter Topology
- Spur Mechanisms
- Spur Consistency and Fractional Spur Optimization
- Phase Resync
- Applications Information
- Outline Dimensions
ADF4150 Data Sheet
Rev. A | Page 8 of 28
Pin No. Mnemonic Description
22 SDV
DD
Power Supply Pin for the Digital Sigma-Delta (Σ-Δ) Modulator. This pin should be the same voltage as AV
DD
.
Decoupling capacitors to the ground plane are to be placed as close as possible to this pin.
23 SD
GND
Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.
24 R
SET
Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage
bias at the R
SET
pin is 0.48 V. The relationship between I
CP
and R
SET
is
SET
CP
R
I
23.7
=
where:
R
SET
= 5.1 kΩ.
I
CP
= 4.65 mA.
25 EP The exposed pad must be connected to GND.