Datasheet

Data Sheet ADF4150
Rev. A | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
CLK
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the three LSBs.
4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. Taking the pin high powers up the device depending on the status of the power-down bits.
5 SW Fastlock Switch. Make a connection to this pin from the loop filter when using the fastlock mode.
6 V
P
Charge Pump Power Supply. This pin should be greater than or equal to AV
DD
. In systems where AV
DD
is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
7 CP
OUT
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter. The output of the loop filter
is connected to V
TUNE
to drive the external VCO.
8 CP
GND
Charge Pump Ground. This is the ground return pin for CP
OUT
.
9 AV
DD
1 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
are to be placed as close as possible to this pin. AV
DD
must have the same value as DV
DD
.
10 RF
IN
+ Input to the RF Input. This small signal input is ac-coupled to the external VCO.
11 RF
IN
− Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 p F.
12, 13 A
GND
Analog Ground. This is a ground return pin for AV
DD
1 and AV
DD
2.
14 RF
OUT
− Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided
down version is available.
15 RF
OUT
+ RF Output. The output level is programmable. The VCO fundamental output or a divided down version is
available.
16 AV
DD
2 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
are to be placed as close as possible to this pin. AV
DD
2 must have the same value as DV
DD
.
17 PDB
RF
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
18 DV
DD
Digital Power Supply. This pin should be the same voltage as AV
DD
. Place decoupling capacitors to the ground
plane as close as possible to this pin.
19 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
20 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of
PLL lock.
21 MUXOUT
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
A
GND
AV
DD
2
DV
DD
REF
IN
SDV
DD
SD
GND
MUXOUT R
SET
RF
OUT
+
RF
OUT
−
PDB
RF
LD
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE
THAT MUST BE CONNECTED TO GND.
PIN 1
INDIC
AT
OR
1
CLK
2
DAT
A
3LE
4CE
5
SW
6
V
P
15
16
17
18
14
13
7CP
OUT
8
CP
GND
9
AV
DD
1
11
RF
IN
–
12A
GND
10
RF
IN
+
21
22
23
24
20
19
ADF4150
T
O
P
VIEW
(Not to Scale)
08226-003