Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Circuit Description
- Register Maps
- Register 0
- Register 1
- Register 2
- Register 3
- Register 4
- Initialization Sequence
- RF Synthesizer—A Worked Example
- Modulus
- Reference Doubler and Reference Divider
- 12-Bit Programmable Modulus
- Cycle Slip Reduction for Faster Lock Times
- Spurious Optimization and Fast lock
- Fast Lock Timer and Register Sequences
- Fast Lock—An Example
- Fast Lock—Loop Filter Topology
- Spur Mechanisms
- Spur Consistency and Fractional Spur Optimization
- Phase Resync
- Applications Information
- Outline Dimensions

Data Sheet ADF4150
Rev. A | Page 5 of 28
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= SD
VDD
= 3.3 V ± 10%; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Operating
temperature range is −40°C to +85°C.
Table 2.
Parameter Limit (B Version) Unit Test Conditions/Comments
t
1
20 ns min LE setup time
t
2
10 ns min DATA to CLK setup time
t
3
10 ns min DATA to CLK hold time
t
4
25 ns min CLK high duration
t
5
25 ns min CLK low duration
t
6
10 ns min CLK to LE setup time
t
7
20 ns min LE pulse width
Figure 2. Timing Diagram
CLK
DATA
LE
LE
DB31 (MSB) DB30
DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
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