Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Circuit Description
- Register Maps
- Register 0
- Register 1
- Register 2
- Register 3
- Register 4
- Initialization Sequence
- RF Synthesizer—A Worked Example
- Modulus
- Reference Doubler and Reference Divider
- 12-Bit Programmable Modulus
- Cycle Slip Reduction for Faster Lock Times
- Spurious Optimization and Fast lock
- Fast Lock Timer and Register Sequences
- Fast Lock—An Example
- Fast Lock—Loop Filter Topology
- Spur Mechanisms
- Spur Consistency and Fractional Spur Optimization
- Phase Resync
- Applications Information
- Outline Dimensions

Data Sheet ADF4150
Rev. A | Page 3 of 28
SPECIFICATIONS
AV
DD
= DV
DD
= SD
VDD
= 3.3 V ± 10%; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. The
operating temperature range is −40°C to +85°C.
Table 1.
Parameter
B Version
Unit Conditions/Comments Min Typ Max
REF
IN
CHARACTERISTICS
Input Frequency 10 250 MHz For f < 10 MHz ensure slew rate > 21 V/µs
Input Sensitivity 0.7 AV
DD
V p-p Biased at AV
DD
/2
1
Input Capacitance 5.0 pF
Input Current ±60 µA
RF INPUT CHARACTERISTICS
RF Input Frequency (RF
IN
), RF Output
Buffer Disabled
0.5 4.0 GHz −10 dBm ≤ RF input power ≤ +5 dBm
RF Input Frequency (RF
IN
), RF Output
Buffer Disabled
0.5 5.0 GHz −5 dBm ≤ RF input power ≤ +5 dBm
RF Input Frequency (RF
IN
) RF Output
Buffer Enabled
0.5 3.5 GHz −10 dBm ≤ RF input power ≤ +5 dBm
RF Input Frequency (RF
IN
) RF Output
Buffer and Dividers Enabled
0.5
3.0
GHz
−10 dBm ≤ RF input power ≤ +5 dBm
Prescaler Output Frequency 750 MHz
MAXIMUM PFD FREQUENCY
Fractional-N (Low Spur Mode) 26 MHz
Fractional-N Mode (Low Noise Mode) 32 MHz
Integer-N Mode 32 MHz
CHARGE PUMP
I
CP
Sink/Source R
SET
= 5.1 kΩ
High Value 4.65 mA
Low Value 0.29 mA
R
SET
Range
2.7
10
kΩ
I
CP
Leakage 1 nA V
CP
= V
P
/2
Sink and Source Current Matching 2 % 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. V
CP
1 % 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. Temperature 2 % V
CP
= V
P
/2
LOGIC INPUTS
Input High Voltage, V
INH
1.5 V
Input Low Voltage, V
INL
0.6 V
Input Current, I
INH
/I
INL
±1 µA
Input Capacitance, C
IN
3.0 pF
LOGIC OUTPUTS
Output High Voltage, V
OH
DV
DD
− 0.4
V
CMOS output chosen
Output High Current, I
OH
500 µA
Output Low Voltage, V
O
0.4 V I
OL
= 500 µA
POWER SUPPLIES
AV
DD
3.0 3.6 V
DV
DD
, SD
VDD
AV
DD
V
P
AV
DD
5.5 V
DI
DD
+ AI
DD
2
50 60 mA
Output Dividers 6 to 24 mA Each output divide by two consumes 6 mA
I
RFOUT
2
24
32
mA
RF output stage is programmable
Low Power Sleep Mode 1 µA