Datasheet

Data Sheet ADF4150
Rev. A | Page 21 of 28
RF SYNTHESIZER—A WORKED EXAMPLE
The following is an example how to program the ADF4150
synthesizer:
RF
OUT
= [INT + (FRAC/MOD)] × [f
PFD
]/RF Divider (3)
where:
RF
OUT
is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
RF Divider is the output divider that divides down the VCO
frequency.
f
PFD
= REF
IN
× [(1 + D)/(R × (1 + T))] (4)
where:
REF
IN
is the reference frequency input.
D is the RF REF
IN
doubler bit.
T is the reference divide-by-2 bit (0 or 1).
R is the RF reference division factor.
For example, in a UMTS system, where 2112.6 MHz RF
frequency output (RF
OUT
) is required, a 10 MHz reference
frequency input (REF
IN
) is available, and a 200 kHz channel
resolution (f
RESOUT
) is required, on the RF output. A 2.1 GHz
VCO would be suitable, but a 4.2 GHz VCO would also be
suitable. In the second case, the RF divider of 2 should be used
(VCO frequency = 4225.2 MHz, RF
OUT
= VCO frequency/RF
divider = 4225.2 MHz/2 = 2112.6 MHz).
It is also important where the loop is closed. In this example, the
loop is closed as depicted in Figure 26 (from the out divider).
Figure 26. Loop Closed Before Output Divider
A channel resolution (f
RESOUT
) of 200 kHz is required at the
output of the RF divider. Therefore, channel resolution at
the output of the VCO (
f
RES
) is to be twice the f
RESOUT
, that
is, 400 kHz.
MOD = REF
IN
/f
RES
MOD = 10 MHz/400 kHz = 25
From Equation 4
f
PFD
= [10 MHz × (1 + 0)/1] = 10 MHz (5)
2112.6 MHz = 10 MHz × (INT + FRAC/25)/2 (6)
where:
INT = 422
FRAC = 13
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REF
IN
) available and the channel resolution (f
RES
) required at
the RF output. For example, a GSM system with 13 MHz REF
IN
sets the modulus to 65. This means the RF output resolution (f
RES
)
is the 200 kHz (13 MHz/65) necessary for GSM. With dither off,
the fractional spur interval depends on the modulus values chosen
(see Table 6).
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important
to note that the PFD cannot operate above 32 MHz due to a
limitation in the speed of the Σ-Δ circuit of the N-divider.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
for the correct operation of the cycle slip reduction (CSR)
function. See the Cycle Slip Reduction for Faster Lock Times
section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4150 allows the
user to program the modulus over a 12-bit range. This means
the user can set up the part in many different configurations for
the application, when combined with the reference doubler and
the 10-bit R counter.
For example, consider an application that requires 1.75 GHz RF
and 200 kHz channel step resolution. The system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz is then fed
into the PFD programming the modulus to divide by 130. This
also results in 200 kHz resolution and offers superior phase
noise performance over the previous setup.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC
and GSM 1800 standards, the programmable modulus is a
great benefit. PDC requires 25 kHz channel step resolution,
whereas GSM 1800 requires 200 kHz channel step resolution.
f
PFD
PFD
VCO
N
DIVIDER
÷2
RF
OUT
08226-022