Datasheet

ADF4150 Data Sheet
Rev. A | Page 16 of 28
Figure 23. Register 3 (R3)
Figure 24. Register 4 (R4)
C2 C1 CLOCK DIVIDER MODE
0
0
CLOCK DIVIDER OFF
0 1 FAST LOCK ENABLE
1
0
RESYNC ENABLE
1
1 RESERVED
D12 D11 .......... D2 D1 CLOCK DIVIDER VALUE
0
0 ..........
0 0
0
0
0
.......... 0
1 1
0 0
..........
1 0
2
0
0 ..........
1
1 3
. .
.......... .
.
.
.
. ..........
.
. .
. .
..........
. .
.
1
1 ..........
0 0
4092
1
1 ..........
0
1 4093
1
1
.......... 1
0 4094
1
1
.......... 1
1
4095
CSR
DB31
DB30 DB29
DB28 DB27
DB26
DB25 DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17 DB16
DB15 DB14
DB13
DB12 DB11
DB10
DB9 DB8
DB7 DB6
DB5
DB4 DB3
DB2 DB1
DB0
0
0 0
0 0
0
0 0
0
F1
0
C2
C1
D12
D11 D10
D9 D8
D7
D6 D5
D4 D3
D2
D1 C3(0)
C2(1) C1(1)
CONTROL
BITS
12-BIT CLOCK DIVIDER VALUE
CLK
DIV
MODE
RESERVED
F1
CYCLE SLIP
REDUCTION
0 DISABLED
1
ENABLED
RESERVED
0
0
RESERVED
08226-019
F3 F2
F2
CHARGE
CANCELLATION
0 DISABLED
1 ENABLED
F3
ANTIBACKLASH
PULSE WIDTH
0 6ns (FRAC-N)
1 3ns (INT_N)
CHARGE CANCEL ABP
D3 RF OUT
0 DISABLED
1 ENABLED
D2 D1 OUTPUT POWER
0 0 –4
0 1 –1
1 0 +2
1 1 +5
D8
MUTE TILL
LOCK DETECT
0 MUTE DISABLED
1 MUTE ENABLED
D12 D11 RF DIVIDER SELECT
0 0 ÷1
0 0 ÷2
0 1 ÷4
0 1 ÷8
D10
0
1
0
1
1 0 ÷160
D13
FEEDBACK
SELECT
0
FUNDAMENTAL
1
DIVIDED
08226-020
OUTPUT
POWER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)
CONTROL
BITS
RESERVED RESERVED
RF OUTPUT ENABLE
MTLD
DIVIDER
SELECT
FEEDBACK SELECT
RESERVED
DBB
2