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Fractional-N/Integer-N PLL Synthesizer

Data Sheet

ADF4150

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FEATURES

Fractional-N synthesizer and integer-N synthesizer

Programmable divide-by-1/-2/-4/-8/-16 output

5.0 GHz RF bandwidth

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Separate charge pump supply (V

) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

3-wire serial interface

Analog and digital lock detect

Switched bandwidth fast-lock mode

Cycle slip reduction

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,

PCS, DCS, DECT)

Test equipment

Wireless LANs, CATV equipment

Clock generation

GENERAL DESCRIPTION

The ADF4150 allows implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers

if used with an external voltage-controlled oscillator (VCO),

loop filter, and external reference frequency.

The ADF4150 is for use with external VCO parts and is

software compatible with the ADF4350. The VCO frequency

can be divided by 1/2/4/8/16 to allow the user to generate RF

output frequencies as low as 31.25 MHz. For applications that

require isolation the RF output stage can be muted. The mute

function is both pin and software controllable.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V and can be powered down when not in use.

The ADF4150 is available in a 4 mm × 4 mm package.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

MUXOUT

OUT

REF

CLK

DATA

SDV

GND

CE CP

GND

SET

OUT

–

PHASE

COMPARATOR

SWITCH

CHARGE

PUMP

OUTPUT

STAGE

INPUT

PDB

MULTIPLEXER

10-BIT R

COUNTER

÷2

DIVIDER

×2

DOUBLER

FUNCTION

LATCH

DATA REGISTER

INTEGER

REG

N COUNTER

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

MULTIPLEXER

LOCK

DETECT

ADF4150

08226-001

DIVIDE-BY-1/

-2/-4/-8/-16

Summary of content (28 pages)

PAGE 1
Fractional-N/Integer-N PLL Synthesizer ADF4150 Data Sheet FEATURES GENERAL DESCRIPTION Fractional-N synthesizer and integer-N synthesizer Programmable divide-by-1/-2/-4/-8/-16 output 5.0 GHz RF bandwidth 3.0 V to 3.6 V power supply 1.
PAGE 2
ADF4150 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 1 ..................................................................................... 18 Applications ....................................................................................... 1 Register 2 ..................................................................................... 18 General Description ........................................
PAGE 3
Data Sheet ADF4150 SPECIFICATIONS AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. The operating temperature range is −40°C to +85°C. Table 1.
PAGE 4
ADF4150 Parameter RF OUTPUT CHARACTERISTICS Minimum Output Frequency Using RF Output Dividers Maximum RFIN Frequency Using RF Output Dividers Harmonic Content (Second) Harmonic Content (Third) Harmonic Content (Second) Harmonic Content (Third) Output Power 3 Output Power Variation Level of Signal With RF Mute Enabled NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 4 Normalized 1/f Noise (PN1_f) 5 Normalized Phase Noise Floor (PNSYNTH)4 Normalized 1/f Noise (PN1_f)5 Spurious Signals Due to PFD
PAGE 5
Data Sheet ADF4150 TIMING CHARACTERISTICS AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is −40°C to +85°C. Table 2.
PAGE 6
ADF4150 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to AVDD Digital I/O Voltage to GND1 Analog I/O Voltage to GND1 REFIN to GND1 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance (Paddle-Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.
PAGE 7
Data Sheet ADF4150 24 23 22 21 20 19 RSET SDGND SDVDD MUXOUT LD REFIN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADF4150 TOP VIEW (Not to Scale) 18 17 16 15 14 13 DVDD PDBRF AVDD2 RFOUT+ RFOUT− AGND NOTES 1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. 08226-003 CPOUT CPGND AVDD1 RFIN+ RFIN– AGND 7 8 9 10 11 12 CLK DATA LE CE SW VP Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 8
ADF4150 Pin No. 22 Mnemonic SDVDD 23 24 SDGND RSET 25 EP Data Sheet Description Power Supply Pin for the Digital Sigma-Delta (Σ-Δ) Modulator. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane are to be placed as close as possible to this pin. Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator. Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at the RSET pin is 0.48 V.
PAGE 9
Data Sheet ADF4150 TYPICAL PERFORMANCE CHARACTERISTICS –60 0 –5 –80 –10 –100 POWER (dBc) –20 –25 –30 –140 –35 –40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (GHz) –180 08226-042 –50 Figure 4. RF Input Sensitivity; RF Output Enabled; Output Divide-by-1 Selected 1k 10k 100k 1M 10M FREQUENCY (Hz) 08226-045 –160 +25°C +85°C –40°C –45 Figure 7.
PAGE 10
Data Sheet –60 –80 –80 –100 –100 –140 –140 –160 –160 –180 1k 10k 100k 1M 10M FREQUENCY (Hz) –180 1k –80 –80 –100 –100 POWER (dBc) –60 –120 –140 –160 –160 FREQUENCY (Hz) 1M 10M –180 1k 08226-039 100k 1M 10M –120 –140 10k 100k Figure 12.
PAGE 11
Data Sheet ADF4150 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION N = INT + FRAC/MOD RF N DIVIDER The reference input stage is shown in Figure 14. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
PAGE 12
ADF4150 Data Sheet MUXOUT AND LOCK DETECT PROGRAM MODES The output multiplexer on the ADF4150 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (for details, see Figure 22). Figure 17 shows the MUXOUT section in block diagram form. Figure 20 through Figure 25 show how the program modes are to be set up in the ADF4150. A number of settings in the ADF4150 are double buffered.
PAGE 13
Data Sheet ADF4150 REGISTER MAPS RESERVED REGISTER 0 16-BIT INTEGER VALUE (INT) CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 DB2 DB1 DB0 C3(0) C2(0) C1(0) PRESCALER REGISTER 1 RESERVED DBR1 12-BIT PHASE VALUE (PHASE) CONTROL BITS DBR
PAGE 14
Data Sheet RESERVED ADF4150 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 N16 N14 N15 N13 N12 N11 N9 N10 N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 DB7 DB6 F4 F5 DB5 DB4 F3 F2 DB3 F1 DB2 DB1 DB0 C3(0) C2(0) C1(0) N16 N15 ... N5 N4 N3 N2 N1 INTEGER VALUE (INT) F12 F11 .......... F2 F1 FRACTIONAL VALUE (FRAC) 0 0 ... 0 0 0 0 0 NOT ALLOWED 0 0 ...
PAGE 15
COUNTER RESET CP THREESTATE POWER-DOWN LDP DBR PD POLARITY DBR 10-BIT R COUNTER CHARGE PUMP CURRENT SETTING LDF MUXOUT RDIV2 LOW NOISE AND LOW SPUR MODES DOUBLE BUFF ADF4150 REFERENCE DOUBLER DBR RESERVED Data Sheet DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 L2 L1 M2 M1 RD2 RD1 R10 RD2 REFERENCE DOUBLER LOW NOISE MODE 0 DISABLED 1 RESERVED 1 ENABLED 0 RESERVED L1 L2 NOISE MODE
PAGE 16
RESERVED CSR CHARGE CANCEL RESERVED RESERVED Data Sheet ABP ADF4150 CLK DIV MODE DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 0 0 F3 F2 0 0 F1 D11 D12 C1 C2 0 D9 D10 DB7 DB6 D6 D7 D8 D5 .......... D2 D1 CLOCK DIVIDER VALUE 0 .......... 0 0 0 0 DISABLED 0 0 .......... 0 1 1 1 ENABLED 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . ..
PAGE 17
ADF4150 LD PIN MODE RESERVED RESERVED Data Sheet RESERVED CONTROL BITS RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 D15 D14 0 0 D1 5 D1 4 LOCK DETECT PIN OPERATION 0 0 LOW 0 1 DIGITAL LOCK DETECT 1 0 LOW 1 1 HIGH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB3 0 DB2 DB1 DB0 C3(1) C2(0) C1(1) 08226-021 0 Figure 25. Register 5 (R5) Rev.
PAGE 18
ADF4150 Data Sheet REGISTER 0 12-Bit Phase Value (Phase) Control Bits These bits control what is loaded as the phase word. The word must be less than the MOD value programmed in Register 1. The word is used to program the RF output phase from 0° to 360° with a resolution of 360°/MOD. See the Phase Resync section for more information. In most applications, the phase relationship between the RF signal and the reference is not important.
PAGE 19
Data Sheet ADF4150 MUXOUT Lock Detect Precision (LDP) The on-chip multiplexer is controlled by Bits[DB28:DB26] (see Figure 22). When DB7 is set to 0, the fractional-N digital lock detect is activated. In this case after setting DB7 to 0, 40 consecutive PFD cycles of 10 ns must occur before digital lock detect is set. When DB7 is programmed to 1, 40 consecutive reference cycles of 6 ns must occur before digital lock detect goes high.
PAGE 20
ADF4150 Data Sheet REGISTER 3 REGISTER 4 Control Bits Control Bits With Bits[C3:C1] set to 0, 1, 1, Register 3 is programmed. Figure 23 shows the input data format for programming this register. With Bits[C3: C1] set to 1, 0, 0, Register 4 is programmed. Figure 24 shows the input data format for programming this register. Antibacklash Pulse Width Feedback Select Setting DB22 to 0 sets the PFD antibacklash pulse width to 6 ns. This is the recommended mode for fractional-N use.
PAGE 21
Data Sheet ADF4150 RF SYNTHESIZER—A WORKED EXAMPLE MODULUS The following is an example how to program the ADF4150 synthesizer: The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fRES) required at the RF output. For example, a GSM system with 13 MHz REFIN sets the modulus to 65. This means the RF output resolution (fRES) is the 200 kHz (13 MHz/65) necessary for GSM.
PAGE 22
ADF4150 Data Sheet A 13 MHz reference signal can be fed directly to the PFD, and the modulus can be programmed to 520 when in PDC mode (13 MHz/520 = 25 kHz). The modulus needs to be reprogrammed to 65 for GSM 1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remain constant (13 MHz). This allows the user to design one loop filter for both setups without running into stability issues.
PAGE 23
Data Sheet ADF4150 FAST LOCK—AN EXAMPLE SPUR MECHANISMS If a PLL has a reference frequency of 13 MHz, fPFD of 13 MHz and a required lock time of 50 µs, the PLL is set to wide bandwidth for 40 µs. This example assumes a modulus of 65 for channel spacing of 200 kHz. This section describes the three different spur mechanisms that arise with a fractional-N synthesizer and how to minimize them in the ADF4150.
PAGE 24
ADF4150 Data Sheet Reference spurs are generally not a problem in fractional-N synthesizers because the reference offset is far outside the loop bandwidth. However, any reference feedthrough mechanism that bypasses the loop can cause a problem. Feedthrough of low levels of on-chip reference switching noise, through the RFIN pin back to the VCO, can result in reference spur levels as high as −90 dBc.
PAGE 25
Data Sheet ADF4150 APPLICATIONS INFORMATION DIRECT CONVERSION MODULATOR The LO ports of the ADL5375 can be driven differentially from the RFOUT+ and RFOUT− outputs of the ADF4150. This gives better performance than a single-ended LO driver and eliminates the use of a balun to convert from a single-ended LO input to the more desirable differential LO inputs for the ADL5375. The typical rms phase noise (100 Hz to 5 MHz) of the LO in this configuration is 0.61°rms.
PAGE 26
ADF4150 Data Sheet INTERFACING ADSP-21xx Interface The ADF4150 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 32 bits that have been clocked into the appropriate register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the register address table. Figure 32 shows the interface between the ADF4150 and a ADSP-21xx digital signal processor.
PAGE 27
Data Sheet ADF4150 There are a number of ways to match the output of the ADF4150 for optimum operation; the most basic is to use a 50 Ω resistor to AVDD. A dc bypass capacitor of 100 pF is connected in series as shown in Figure 33. Because the resistor is not frequency dependent, this provides a good broadband match. The output power in this circuit into a 50 Ω load typically gives values chosen by Bits[DB4:DB3] in Register 4 (R4).
PAGE 28
ADF4150 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 13 12 2.65 2.50 SQ 2.45 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 04-12-2012-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 35.