Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Circuit Description
- Register Maps
- Register 0
- Register 1
- Register 2
- Register 3
- Register 4
- Initialization Sequence
- RF Synthesizer—A Worked Example
- Modulus
- Reference Doubler and Reference Divider
- 12-Bit Programmable Modulus
- Cycle Slip Reduction for Faster Lock Times
- Spurious Optimization and Fast lock
- Fast Lock Timer and Register Sequences
- Fast Lock—An Example
- Fast Lock—Loop Filter Topology
- Spur Mechanisms
- Spur Consistency and Fractional Spur Optimization
- Phase Resync
- Applications Information
- Outline Dimensions

Data Sheet ADF4150
Rev. A | Page 27 of 28
OUTPUT MATCHING
There are a number of ways to match the output of the ADF4150
for optimum operation; the most basic is to use a 50 Ω resistor to
AV
DD
. A dc bypass capacitor of 100 pF is connected in series as
shown in Figure 33. Because the resistor is not frequency
dependent, this provides a good broadband match. The output
power in this circuit into a 50 Ω load typically gives values
chosen by Bits[DB4:DB3] in Register 4 (R4).
Figure 33. Simple ADF4150 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to AV
DD
. This gives a better match and, therefore, more
output power.
Experiments indicate that the circuit shown in Figure 34
provides an excellent match to 50 Ω for the W-CDMA UMTS
Band 1 (2110 MHz to 2170 MHz). The maximum output power
in that case is about 7 dBm. Both single-ended architectures can
be examined using the EVAL-ADF4150EB1Z evaluation board.
Figure 34. Optimum ADF4150 Output Stage
If differential outputs are not needed, the unused output can be
terminated or combined with both outputs using a balun.
08226-029
50Ω
100pF
RF
OUT
A
V
DD
50Ω
3.9nH
1nF
RF
OUT
AV
DD
50Ω
08226-030