Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Functional Block Diagram
- Revision History
- Specifications
- Absolute Maximum Ratings
- Pin Configuration and Function Descriptions
- Typical Performance Characteristics
- Circuit Description
- Register Maps
- Register 0
- Register 1
- Register 2
- Register 3
- Register 4
- Initialization Sequence
- RF Synthesizer—A Worked Example
- Modulus
- Reference Doubler and Reference Divider
- 12-Bit Programmable Modulus
- Cycle Slip Reduction for Faster Lock Times
- Spurious Optimization and Fast lock
- Fast Lock Timer and Register Sequences
- Fast Lock—An Example
- Fast Lock—Loop Filter Topology
- Spur Mechanisms
- Spur Consistency and Fractional Spur Optimization
- Phase Resync
- Applications Information
- Outline Dimensions

Data Sheet ADF4150
Rev. A | Page 15 of 28
Figure 22. Register 2 (R2)
RD2
RE
F
ER
ENC
E
D
O
UB
L
ER
0
DI
S
ABL
ED
1 ENABLED
RD
1
R
E
F
E
R
E
NCE
D
IV
ID
E
BY
2
0
DI
SAB
L
ED
1
E
NAB
L
ED
CP4 CP3 CP2 CP1
I
C
P
(mA)
4.7kΩ
0 0 0 0 0
.
31
0 0 0 1 0
.63
0
0
1
0 0
.94
0
0 1
1 1.25
0 1 0 0 1.56
0 1 0 1 1.88
0
1
1
0
2
.19
0
1 1 1 2.50
1
0 0 0 2.81
1
0
0 1
3.13
1
0 1 0
3.44
1
0 1 1
3
.75
1
1 0 0
4.06
1 1
0 1 4
.38
1
1 1 0
4.69
1 1 1 1
5
.00
R10 R9 ....
..
....
..........
......
....
..........
....
....
..
..........
......
..
..
......
....
....
......
........
..
R
2 R
1
R D
IV
I
DER
(
R
)
0
0 0
1 1
0 0 1 0 2
.
.
.
.
.
.
. . . .
. . .
. .
1
1 0 0
1020
1
1 0
1 1021
1
1 1 0
1022
1 1
1 1 102
3
DB31
DB3
0 DB2
9
DB28
DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB1
9
DB18
DB17
DB1
6 DB1
5 DB1
4
DB13
DB1
2
DB1
1
DB1
0
DB9
DB8
DB
7 DB
6 DB
5
DB4 DB3 DB2 DB1 DB0
0 L2 L1 M3 M2 M1 RD2 RD1 R10 R
9
R8
R7
R
6 R
5
R4
R3
R
2
R
1
D
1 C
P4
CP3
CP2
C
P1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(
0)
RDIV2 DB
R
REFERENCE
DOUBLER
DBR
CHARGE
PUMP
CURRENT
SETTING
10-BIT R COUN
T
ER DB
R
C
ONTROL
BITS
LDP
PD
POLARITY
POWER-DOWN
CP THREE-
STATE
COUNTER
RESET
LDF
MU
X
OU
T
DOUBLE BUFF
U
5
LDP
0 10ns
1 6ns
U
4
P
D
P
OL
AR
ITY
0 NEGATIVE
1
P
O
S
ITI
VE
U3
P
OWE
R
-D
OWN
0 DISAB
L
ED
1 ENABLED
U2
CP
T
HREE-S
T
A
T
E
0
DI
S
ABL
ED
1
E
NAB
L
ED
U1
CO
UN
TER
RESET
0
DI
S
ABL
ED
1
E
NAB
L
ED
D
1
D
O
UB
L
E
BU
FF
E
R
R4
DB22
:DB2
0
0
D
I
S
AB
L
ED
1 E
NABL
ED
U6 LDF
0
FRAC
-N
1 INT-N
RESERVED
M3 M2 M1 O
UTP
UT
0 0
0 T
HREE-ST
ATE O
UTPUT
0
0 1
DV
DD
0 1
0 DGND
0 1 1
R DIVIDER O
UTP
UT
1
0 0 N DIVIDER
OUTP
UT
1
0 1
ANALOG LOCK
DETECT
1 1 0 DIGIT
AL LOCK D
ET
E
CT
1 1 1 RESER
VED
L1
L
2 N
OISE
MODE
0 0 LOW NOISE
M
OD
E
0 1 RESERVED
1 0 RESERVED
1 1 LOW SPUR MODE
LOW
NOISE AND
LOW SPUR
MODES
08226-018