Datasheet

ADF4116/ADF4117/ADF4118
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= 3 V ± 10%, 5 V ± 10%; AV
DD
≤ V
P
< 6.0 V; AGND = DGND = CPGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Guaranteed by design, but not production tested.
Table 2.
Parameter Limit at T
MIN
to T
MAX
(B, Y Version) Unit Test Conditions/Comments
t
1
10 ns min DATA to CLK setup time
t
2
10 ns min DATA to CLK hold time
t
3
25 ns min CLK high duration
t
4
25 ns min CLK low duration
t
5
10 ns min CLK to LE setup time
t
6
20 ns min LE pulse width
CLK
DAT
A
LE
LE
DB20 (MSB) DB19 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
5
t
2
t
4
t
6
t
1
t
3
00392-002
Figure 2. Timing Diagram