Datasheet

Data Sheet ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 15 of 28
Table 7. Reference Counter Latch Map
OPERATION
LDP
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
0
1
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
R14
0
0
0
0
•
•
•
1
1
1
1
R13
0
0
0
0
•
•
•
1
1
1
1
R12
0
0
0
0
•
•
•
1
1
1
1
R3
0
0
0
1
•
•
•
1
1
1
1
R2
0
1
1
0
•
•
•
0
0
1
1
R1
1
0
1
0
•
•
•
0
1
0
1
DIVIDE RATIO
1
2
3
4
•
•
•
16380
16381
16382
16383
••••••••••
••••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
•••••••••
•
••
••••••• •
••••••••• •
••••••••• •
••••••••• •
••••••••• •
TEST
MODE BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB13
LDP T2 T1 R14 R13 R12 R11 R10 R8
R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)R9
14-BIT REFERENCE COUNTER
CONTROL
BITS
DEVRE
S
E
R
DB2
DB1
DB0
SYNCDLY ABP2 ABP1
ANTI-
BACKLASH
WIDTH
SYNC
DLY
KCOL
TC
ETED
NOISICER
P
ABP1ABP2
0
0
1
1
0
1
0
1
3.0ns
1.5ns
6.0ns
3.0ns
ANTIBACKLASH PULSE WIDTH
SYNCDLY
0
0
1
1
0
1
0
1
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
OPERATION
X
X = DON'T
CARE
03496-0-034