Datasheet

ADF4107 Data Sheet
Rev. D | Page 12 of 20
REFERENCE COUNTER LATCH MAP
LD
P
0
1
ABP2 ABP1
0 0 2.9ns
0
1 1.3ns TEST MODE ON
LY
. DO NOT USE
1
0 6.0ns
1
1 2.9ns
R14
R13
R12 ..........
R3
R2 R1
0
0
0 ..........
0 0 1 1
0 0 0 .......... 0
1
0
2
0
0 0
.......... 0 1 1
3
0 0 0 .......... 1
0 0
4
.
.
.
.......... .
. . .
. .
.
..........
.
. .
.
. . . ..........
.
.
.
.
1 1 1
..........
1
0
0
16380
1 1 1 ..........
1
0
1
16381
1 1 1 ..........
1 1
0
16382
1
1 1
.......... 1
1
1 16383
X = DON’T CARE
DB20
DB19 DB18
DB17 DB16
DB15 DB14 DB13
DB12 DB
11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 DB0
C2
(0)
C1
(0)
R1R2
R3R4R5R6R7R8
R9
R10
R
1
1
R12
R13
R14
ABP1
ABP2
T1
T2
LD
P
DB21
DB22
DB23
0
0
X
RESE
R
VED
LOCK
DETECT
PRECISION
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTRO
L
BITS
DIVIDE R
A
TIO
ANTIBACKLASH PULSE WIDTH
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMA
L
OPER
ATION.
OPER
ATION
THREE CONSECUTIVE CYCLES OF PHASE DEL
A
Y LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELA
Y LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET
.
BOTH OF THESE BITS
MUST BE SET T
O 0 FOR
NORMAL OPERATION.
03338-023
Figure 23. Reference Counter Latch Map