Datasheet

Data Sheet ADF4106
Rev. E | Page 13 of 24
Table 7. Reference Counter Latch Map
LDP
0
1
ABP2 ABP1
0 0 2.9ns
0 1 1.3ns
1 0 6.0ns
1 1 2.9ns
R14 R13
R12 .......... R3 R2 R1
0 0 0 .......... 0 0 1 1
0 0 0
..........
0 1 0 2
0
0 0 .......... 0 1 1 3
0 0 0 .......... 1 0 0
4
. . . .......... . . .
.
. . . .......... .
. .
.
.
.
. .......... . . . .
1 1 1 .......... 1 0
0 16380
1 1 1 .......... 1 0 1 16381
1 1 1 .......... 1 1 0
16382
1 1 1 .......... 1 1 1 16383
X
= DON’
T CARE
DB20
DB19
DB18
DB17 DB16
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2 DB1 DB0
C2 (0) C1 (0)R1R2R3R4R5R6R7
R8R9
R10R11
R12R13R14ABP1ABP2T1T2LDP
DB21DB22DB23
0 0
X
RESERVED
LOCK
DETECT
PRECISION
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DIVIDE RATIO
ANTIBACKLASH PULSE WIDTH
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
02720-023