Datasheet

ADF4002 Data Sheet
Rev. C | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
R
SET
C
P
CPGND
AGND
MUXOUT
LE
D
AT
A
CLK
CE
DGND
16
15
14
13
12
1
1
10
9
1
2
3
4
5
6
7
8
RF
IN
B
RF
IN
A
A
V
DD
REF
IN
V
P
DV
DD
ADF4002
T
O
P
VIEW
(Not to Scale)
06052-002
PIN 1
INDICATOR
Figure 3. TSSOP Pin Configuration (Top View)
15 MUXOUT
14 LE
13 D
AT
A
12 CLK
CPGND 1
AGND 2
AGND 3
20 C
P
1
1 CE
6 7 8
DGND 9
DGND 10
4
5
19 18 17 16
RF
IN
B
RF
IN
A
R
SET
V
P
DV
DD
DV
DD
AV
DD
A
V
DD
REF
IN
PIN 1
INDICATOR
ADF4002
T
O
P
VIEW
(Not to Scale)
06052-003
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
Figure 4. LFCSP Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
SET
MAXCP
R
I
25.5
=
where R
SET
= 5.1 kΩ and I
CP MAX
= 5 mA.
2 20 CP Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter that, in turn, drives the
external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the RF input.
5 4 RF
IN
B Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 11.
6 5 RF
IN
A Input to the RF Input. This small signal input is ac-coupled to the external VCO.
7 6, 7 AV
DD
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to the AV
DD
pin. AV
DD
must be the same value as DV
DD
.
8 8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can
be ac-coupled.
9
9, 10
DGND
Digital Ground.
10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit F2.
11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches; the latch is selected using the control bits.
14 15 MUXOUT Multiplexer Output. This allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
15
16, 17
DV
DD
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
16 18 V
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it can
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
EP Exposed Pad. The exposed pad must be connected to AGND.