Datasheet

ADF4002 Data Sheet
Rev. C | Page 4 of 20
B Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PN
SYNTH
)
6
−222 dBc/Hz PLL loop bandwidth = 500 kHz, measured at 100 kHz
offset
Normalized 1/f Noise (PN
1_f
)
7
−119 dBc/Hz 10 kHz offset; normalized to 1 GHz
1
Operating temperature range (B version) is −40°C to +85°C.
2
AV
DD
= DV
DD
= 3 V.
3
AC coupling ensures AV
DD
/2 bias.
4
Guaranteed by design. Sample tested to ensure compliance.
5
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; RF
IN
= 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN
frequency in MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value)
and 10 logF
PFD
. PN
SYNTH
= PN
TOT
– 10 logF
PFD
– 20 logN.
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f
RF
,
and at a frequency offset, f, is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(f
RF
/1 GHz). All phase noise measurements were performed with the EV-ADF4002SD1Z and the
Agilent E5500 phase noise system. Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MAX
to T
MIN
,
unless otherwise noted.
1
Table 2.
Parameter Limit (B Version)
2
Unit Test Conditions/Comments
t
1
10 ns min DATA to CLK setup time
t
2
10 ns min DATA to CLK hold time
t
3
25 ns min CLK high duration
t
4
25 ns min CLK low duration
t
5
10 ns min CLK to LE setup time
t
6
20 ns min LE pulse width
1
Guaranteed by design, but not production tested.
2
Operating temperature range (B version) is −40°C to +85°C.
Timing Diagram
CLK
DB22
DB2
DATA
LE
t
1
LE
DB23 (MSB)
t
2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
3
t
4
t
6
t
5
06052-022
Figure 2. Timing Diagram