Datasheet

Data Sheet ADF4002
Rev. C | Page 3 of 20
SPECIFICATIONS
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPG N D = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω,
T
A
= T
MAX
to T
MIN
, unless otherwise noted.
Table 1.
B Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
RF CHARACTERISTICS See Figure 11 for input circuit
RF Input Sensitivity −10 0 dBm
RF Input Frequency (RF
IN
) 5 400 MHz For RF
IN
< 5 MHz, ensure slew rate (SR) > 4 V/µs
REFIN CHARACTERISTICS
REFIN Input Frequency 20 300 MHz For REFIN < 20 MHz, ensure SR > 50 V/µs
REFIN Input Sensitivity
2
0.8 V
DD
V p-p Biased at AV
DD
/2
3
REFIN Input Capacitance 10 pF
REFIN Input Current ±100 µA
PHASE DETECTOR
Phase Detector Frequency
4
104
MHz
ABP = 0, 0 (2.9 ns antibacklash pulse width)
CHARGE PUMP Programmable, see Figure 18
I
CP
Sink/Source
High Value
5
mA
With R
SET
= 5.1 kΩ
Low Value 625 µA
Absolute Accuracy 2.5 % With R
SET
= 5.1 kΩ
R
SET
Range 3.0 11 kΩ See Figure 18
I
CP
Three-State Leakage 1 nA T
A
= 25°C
I
CP
vs. V
CP
1.5 % 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
Sink and Source Current Matching 2 % 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. Temperature 2 % V
CP
= V
P
/2
LOGIC INPUTS
V
IH
, Input High Voltage 1.4 V
V
IL
, Input Low Voltage 0.6 V
I
INH
, I
INL
, Input Current ±1 µA
C
IN
, Input Capacitance 10 pF
LOGIC OUTPUTS
V
OH
, Output High Voltage 1.4 V Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V
V
OH
, Output High Voltage V
DD
− 0.4 V CMOS output chosen
I
OH
100 µA
V
OL
, Output Low Voltage 0.4 V I
OL
= 500 µA
POWER SUPPLIES
AV
DD
2.7 3.3 V
DV
DD
AV
DD
V
P
AV
DD
5.5 V AV
DD
≤ V
P
≤ 5.5 V
I
DD
5
(AI
DD
+ DI
DD
) 5.0 6.0 mA
I
P
0.4 mA T
A
= 25°C
Power-Down Mode 1 µA AI
DD
+ DI
DD