Datasheet

Data Sheet ADF4002
Rev. C | Page 13 of 20
FUNCTION LATCH MAP
PD2 PD1
MODE
0
X
X
1
X 0
1 0 1
1 1
1
CPI6 CPI5 CP14
CPI3 CPI2
CPI1
3kΩ 5.1kΩ 1
1kΩ
0 0 0
0
0 1
0 1 0
0 1 1
1 0
0
1 0 1
1
1 0
1 1 1
TC4
TC3 TC2
TC1
0 0 0
0 3
0 0 0
1 7
0 0
1
0 11
0
0 1 1
15
0
1 0 0
19
0 1 0
1
23
0
1 1 0 27
0
1 1 1
31
1 0 0
0 35
1 0
0 1
39
1 0
1 0 43
1
0 1
1 47
1 1 0
0 51
1 1
0 1 55
1
1 1 0
59
1
1 1 1 63
F4
0
1
1
M3 M2 M1
0
0 0
0 0
1
0
1 0
0 1
1
1 0
0
1
0 1
1 1
0
1
1 1
F3
0
1
F2
0
1
F1
0
1
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB
1
1
DB10
DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2
DB1
DB0
C2
(1)
C1
(0)
F1
PD1
M1
M2
M3
F3
X
X CPI1CPI2CPI5
CPI6
TC4
PD2
F2CPI3CPI4
DB21
TC3
TC2
TC1
DB22DB23
F4
F5
THREE-STATE
F5
X
0
1
NEGATIVE
POSITIVE
RESE
R
VED
POWER-
DOWN 2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTRO
L
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREE-
S
TATE
MUXOUT
CONTRO
L
POWER-
DOWN 1
COUNTER
RESET
CONTRO
L
BITS
PHASE DETEC
T
OR
POLARITY
COUNTER
OPER
A
TION
NORMA
L
R COUNTER
AND
N COUNTER
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
FASTLOCK DISABLED
F
ASTLOCK MODE 1
FASTLOCK MODE 2
F
ASTLOCK MODE
THREE-STA
TE OUTPUT
DIGIT
A
L LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
N-CHANNE
L
OPEN-DRAIN
LOCK DETECT
SERIA
L
DAT
A OUTPUT
DGND
OUTPUT
TIMEOUT
(PFD CYCLES)
I
CP
(mA)
ASYNCHRONOUS POWER-DOWN
NORMAL OPER
ATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
CE PIN
PD
POLARITY
06052-017
THESE BITS ARE NOT USED
BY
THE DEVICE AND ARE
DON'T CARE BITS.
1.088
2.176
3.264
4.352
5.440
6.528
7.616
8.704
0.625
1.250
1.875
2.500
3.125
3.750
4.375
5.000
0.294
0.588
0.882
1.176
1.470
1.764
2.058
2.352
SEE PAGE 15
Figure 18. Function Latch Map