Datasheet

REV.
ADF4001
–8–
Table III. Reference Counter Latch Map
LDP OPERATION
0THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
002.9ns
011.3ns
106.0ns
112.9ns
R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO
000.......... 0011
000.......... 0102
000.......... 0113
000.......... 1004
............. ....
............. ....
............. ....
111.......... 10016380
111.......... 10116381
111.......... 11016382
111.......... 11116383
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)R1R2R3R4R5R7R14ABP1T2LDP R13 R6
CONTROL
BITS
ABP2
T1
DB21
R12 R11 R10
DB22DB23
R8R9
RESERVED
LOCK
DETECT
PRECISION
TEST
MODE
BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
XXX
X = DON’T CARE
B