Datasheet
REV.
ADF4001
–7–
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
DGND
DV
DD
CONTROL MUXOUT
MUX
Figure 6. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect. Digital lock detect is
active high. When LDP in the R counter latch is set to 0, digital
lock detect is set high when the phase error on three consecutive
phase detector cycles is less than 15 ns. With LDP set to 1, five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
25 ns is detected on any subsequent PD cycle. The N-channel
open-drain analog lock detect should be operated with an external
pull-up resistor of 10 kΩ nominal. When lock has been detected,
this output will be high with narrow low-going pulses.
INPUT SHIFT REGISTER
The ADF4001 digital section includes a 24-bit input shift regis-
ter, a 14-bit R counter, and a 13-bit N counter. Data is clocked
into the 24-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in the timing diagram of Figure 1. The truth
table for these bits is shown in Table I. Table II shows a sum-
mary of how the latches are programmed.
Table I. C2, C1 Truth Table
Control Bits
C2 C1 Data Latch
00R Counter
01N Counter
10Function Latch
11Initialization Latch
Table II. ADF4001 Family Latch Summary
REFERENCE COUNTER LATCH
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)R1R2R3R4R5R7R14ABP1T2LDP R13 R6
CONTROL
BITS
ABP2
T1
DB21
R12 R11 R10
DB22DB23
R8R9
RESERVED
LOCK
DETECT
PRECISION
TEST
MODE
BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
XXX
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (1)F1PD1M1M2M3F3CPI1CPI2CPI5CPI6 TC4PD2 F2
CONTROL
BITS
COUNTER
RESET
POWER-
DOWN 1
MUXOUT
CONTROL
PHASE
DETECTOR
POLARITY
CP
THREE-
STATE
POWER-
DOWN 2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
CPI3CPI4
DB21
CURRENT
SETTING
2
TC3 TC2 TC1
DB22DB23
FASTLOCK
ENABLE
FASTLOCK
MODE
F4F5
RESERVED
X = DON’T CARE
XX
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0)
C1 (1)
N1
N8N9N12N13 N7G1
CONTROL
BITS
N10N11
DB21
N6 N5 N4
DB22DB23
N2
N3
RESERVED
CP
GAIN
RESERVED
13-BIT N COUNTER
XX
XXXXXX
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)F1PD1M1M2M3F3CPI1CPI2CPI5CPI6 TC4PD2 F2
CONTROL
BITS
COUNTER
RESET
POWER-
DOWN 1
MUXOUT
CONTROL
PHASE
DETECTOR
POLARITY
CP
THREE-
STATE
POWER-
DOWN 2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
CPI3CPI4
DB21
CURRENT
SETTING
2
TC3 TC2 TC1
DB22DB23
FASTLOCK
ENABLE
FASTLOCK
MODE
F4F5
RESERVED
XX
N COUNTER LATCH
FUNCTION LATCH
INITIALIZATION LATCH
B