Datasheet
ADF4001
Rev. B | Page 4
PIN CONFIGURATIONS
TSSOP
LFCSP
Table 1. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No. Mnemonic Description
1 19 R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump
output current. The nominal voltage potential at the R
SET
pin is 0.66 V. The relationship
between I
CP
and R
SET
is
SET
MAXCP
R
I
5.23
So, with R
SET
= 4.7 kΩ, I
CP MAX
= 5 mA.
2 20 CP
Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter which,
in turn, drives the external VCO or VCXO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RF
IN
B
Complementary Input to the N counter. This point must be decoupled to the ground
plane with a small bypass capacitor, typically 100 pF. See Figure 3.
6 5 RF
IN
A Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
7 6, 7 AV
DD
Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
DD
must have the
same value as DV
DD
.
8 8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc
equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL
or CMOS crystal oscillator or can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump
output into three-state mode. Taking the pin high will power up the device, depending on
the status of the power-down bit F2.
11 12 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected by using the control bits.
14 15 MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15 16, 17 DV
DD
Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
digital ground plane should be placed as close as possible to this pin. DV
DD
must be the
same value as AV
DD
.
16 18 V
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems
where V
DD
is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning
range of up to 5 V.
N/A EP EPAD Exposed Pad. The exposed pad should be connected to AGND.
R
SET
CP
CPGND
AGND
RF
IN
B
RF
IN
A
AV
DD
REF
IN
LE
MUXOUT
DV
DD
V
P
CE
CLK
DATA
DGND
NOTES
1. TRANSISTOR COUNT 6425 (CMOS)
AND 50 (BIPOLAR).
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
ADF4001
16
15
14
13
12
11
10
9
02569-003
AGND
MUXOUT
LE
DATA
CLK
CE
AV
DD
AV
DD
REF
IN
DGND
DGND
CP
R
SET
V
P
DV
DD
DV
DD
CPGND
AGND
RF
IN
B
RF
IN
A
NOTES
1. TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR).
2. CONNECT EXPOSED PAD TO AGND.
14
13
12
1
3
4
15
11
2
5
7
6
8
9
10
19
20
18
17
16
ADF4001
TOP VIEW
(Not to Scale)
02569-004