Datasheet
REV.
–2–
ADF4001–SPECIFICATIONS
1
(AV
DD
= DV
DD
= 3 V 10%, 5 V 10%; AV
DD
≤ V
P
≤ 6.0 V
; AGND = DGND =
CPGND = 0 V; R
SET
= 4.7 k; T
A
= T
MIN
to T
MAX
, unless otherwise noted; dBm referred to 50 .)
Parameter B Version Unit Test Conditions/Comments
RF CHARACTERISTICS (3 V) See Figure 3 for Input Circuit
RF Input Frequency 5/165 MHz min/max
RF Input Sensitivity –10/0 dBm min/max
RF CHARACTERISTICS (5 V)
RF Input Frequency 10/200 MHz min/max –5/0 dBm min/max
20/200 MHz min/max –10/0 dBm min/max
REF
IN
CHARACTERISTICS See Figure 2 for Input Circuit
REF
IN
Input Frequency 5/104 MHz min/max For f < 5 MHz, Use DC-Coupled Square Wave
(0 to V
DD
)
REF
IN
Input Sensitivity
2
–5 dBm min AC-Coupled. When DC-Coupled:
0 to V
DD
Max (CMOS Compatible)
REF
IN
Input Capacitance 10 pF max
REF
IN
Input Current ± 100 µA max
PHASE DETECTOR
Phase Detector Frequency
3
55 MHz max
CHARGE PUMP
I
CP
Sink/Source Programmable: See Table V
High Value 5 mA typ With R
SET
= 4.7 kΩ
Low Value 625 µA typ
Absolute Accuracy 2.5 % typ With R
SET
= 4.7 kΩ
R
SET
Range 2.7/10 kΩ typ See Table V
I
CP
Three-State Leakage Current 1 nA typ
Sink and Source Current Matching 2 % typ 0.5 V ≤ V
CP
≤ V
P
– 0.5
I
CP
vs. V
CP
1.5 % typ 0.5 V ≤ V
CP
≤ V
P
– 0.5
I
CP
vs. Temperature 2 % typ V
CP
= V
P
/2
LOGIC INPUTS
V
INH
, Input High Voltage 0.8 × DV
DD
V min
V
INL
, Input Low Voltage 0.2 × DV
DD
V max
I
INH
/I
INL
, Input Current ± 1 µA max
C
IN
, Input Capacitance 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage DV
DD
– 0.4 V min I
OH
= 500 µA
V
OL
, Output Low Voltage 0.4 V max I
OL
= 500 µA
POWER SUPPLIES
AV
DD
2.7/5.5 V min/V max
DV
DD
AV
DD
V
P
AV
DD
/6.0 V min/V max AV
DD
≤ V
P
≤ 6.0 V
I
DD
4
(AI
DD
+ DI
DD
)
ADF4001 5.5 mA max 4.5 mA typical
I
P
0.4 mA max T
A
= 25°C
Low Power Sleep Mode 1 µA typ
NOISE CHARACTERISTICS
ADF4001 Phase Noise Floor
5
–161 dBc/Hz typ @ 200 kHz PFD Frequency
–153 dBc/Hz typ @ 1 MHz PFD Frequency
Phase Noise Performance
6
@ VCXO Output
200 MHz Output
7
–99 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
Spurious Signals
200 MHz Output
7
–90/–95 dBc typ/dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1
Operating temperature range (B Version) is –40°C to +85°C.
2
AV
DD
= DV
DD
= 3 V; for AV
DD
= DV
DD
= 5 V, use CMOS compatible levels.
3
Guaranteed by design. Sample tested to ensure compliance.
4
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; RF
IN
= 100 MHz.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6
The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.
7
f
REF
IN
= 10 MHz; f
PFD
= 200 kHz; Offset Frequency = 1 kHz; f
RF
= 200 MHz; N = 1000; Loop B/W = 20 kHz.
Specifications subject to change without notice.
B