Datasheet

Data Sheet ADE9153A
Rev. 0 | Page 7 of 50
SPI TIMING CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit
SS to SCLK Edge
t
SS
10 ns
SCLK Frequency f
SCLK
10 MHz
SCLK Low Pulse Width t
SL
40 ns
SCLK High Pulse Width t
SH
40 ns
Data Output Valid After SCLK Edge t
DAV
40 ns
Data Input Setup Time Before SCLK Edge t
DSU
10 ns
Data Input Hold Time After SCLK Edge t
DHD
10 ns
Data Output Fall Time t
DF
10 ns
Data Output Rise Time t
DR
10 ns
SCLK Fall Time t
SF
10 ns
SCLK Rise Time t
SR
10 ns
MISO Disable After SS Rising Edge
t
DIS
100 ns
SS High After SCLK Edge
t
SFS
0 ns
MSB LSB
LSB IN
INTERMEDIATE BITS
INTERMEDIATE BITS
t
SFS
t
DIS
t
SS
t
SL
t
DF
t
SH
t
DHD
t
DAV
t
DSU
t
SR
t
SF
t
DR
MSB IN
MOSI
MISO
S
CL
K
SS
16519-002
Figure 2. SPI Interface Timing Diagram
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.