Datasheet
ADE9153A Data Sheet
Rev. 0 | Page 40 of 50
Addr. Name Bits Bit Name Settings Description Reset Access
2 REVRPA
This bit indicates if the
Phase A fundamental
reactive power changed
sign. This bit is updated
when the power value in
the AFVAR_ACC register
updates, after PWR_TIME
4 kSPS samples.
0x0 R/W1
1 Reserved Reserved. 0x0 R
0 REVAPA
This bit indicates if the
Phase A total active power
changes sign. See the
REVRPA description.
0x0 R/W1
0x405 Mask 31 CHIP_STAT
Set this bit to enable an
interrupt when any bit in
the CHIP_STATUS register is
set.
0x0 R
30 EVENT_STAT
Set this bit to enable an
interrupt when any bit in
the EVENT_STATUS register
is set.
0x0 R/W
29 MS_STAT
Set this bit to enable an
interrupt when any bit in the
MSURE_STATUS_IRQ register
is set.
0x0 R/W
[28:26] Reserved Reserved. 0x0 R
25 PF_RDY
Set this bit to enable an
interrupt when the power
factor measurements
update, every 1.024 sec.
0x0 R/W
24 CRC_CHG
Set this bit to enable an
interrupt if any of the
registers monitored by the
configuration register CRC
change value. The CRC_RSLT
register holds the new
configuration register CRC
value.
0x0 R/W
23 CRC_DONE
Set this bit to enable an
interrupt when the
configuration register CRC
calculation is complete,
after being initiated by
writing the
FORCE_CRC_UPDATE bit in
the CRC_FORCE register.
0x0 R/W
22 Reserved Reserved. 0x0 R
21 ZXTOAV
Set this bit to enable an
interrupt when there is a
zero-crossing timeout on
the voltage channel; this
means that a zero crossing
on the voltage channel is
missing.
0x0 R/W
20 ZXBI
Set this bit to enable an
interrupt when a zero
crossing is detected on
Current Channel B.
0x0 R/W
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