Datasheet
ADE9153A Data Sheet
Rev. 0 | Page 38 of 50
Addr. Name Bits Bit Name Settings Description Reset Access
0x402 Status 31 CHIP_STAT
When set, this indicates a bit
in the CHIP_STATUS register
is set. This bit is cleared
when CHIP_STATUS is read.
0x0 R
30 EVENT_STAT
When set, this indicates a bit
in the EVENT_STATUS register
is set. This bit is cleared when
EVENT_STATUS is read.
0x0 R
29 MS_STAT
When set, this indicates a bit
in the MS_STATUS_IRQ
register is set. This bit is
cleared when MS_STATUS_
IRQ is read.
0x0 R
[28:26] Reserved Reserved. 0x0 R
25 PF_RDY
This bit goes high to
indicate when the power
factor measurements are
updated, every 1.024 sec.
0x0 R/W1
24 CRC_CHG
This bit is set if any of the
registers monitored by the
configuration register CRC
change value. The CRC_RSLT
register holds the new
configuration register CRC
value.
0x0 R/W1
23 CRC_DONE
This bit is set to indicate
when the configuration
register CRC calculation is
complete, after being
initiated by writing to the
FORCE_CRC_UPDATE bit in
the CRC_FORCE register.
0x0 R/W1
22 Reserved Reserved. 0x0 R
21 ZXTOAV
This bit is set to indicate a
zero-crossing timeout on
the voltage channel; this
means that a zero crossing
on the voltage channel is
missing.
0x0 R/W1
20 ZXBI
This bit is set to 1 to indicate
that a zero crossing is
detected on Current
Channel B.
0x0 R/W1
19 ZXAI
This bit is set to 1 to indicate
that a zero crossing is
detected on Current
Channel A.
0x0 R/W1
18 Reserved Reserved. 0x0 R
17 ZXAV
This bit is set to 1 to indicate
that a zero crossing is
detected on Voltage
Channel.
0x0 R/W1
16 RSTDONE
This bit is set to indicate that
the IC finished the power-up
sequence after a reset,
which means that the user
can configure the IC via the
SPI port or UART.
0x0 R/W1
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