Datasheet

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Data Sheet ADE9153A

Rev. 0 | Page 29 of 50

APPLICATIONS INFORMATION

INTERRUPTS/EVENTS

The ADE9153A has two pins,

IRQ

and ZX/DREADY/CF2, that

can be used as interrupts to the host processor.

IRQ PIN INTERRUPTS

The

IRQ

pin goes low when an enabled interrupts occurs and stays

low until the event is acknowledged by setting the corresponding

status bit in the status register. The bits in the mask register

configure the respective interrupts.

SERVICING INTERRUPTS

Interrupts in the ADE9153A are in a tiered system where it

never takes more than two communications to clear an interrupt.

The status register is a Tier 1 interrupt register and CHIP_STATUS,

EVENT_STATUS, and MS_STATUS_IRQ are Tier 2 interrupt

registers, which correspond to the status bits, CHIP_STAT,

EVENT_STAT, and MS_STAT.

For the Tier 1 status register bits, Bits[25:0],

1. Read the status register to see which bit is set.

2. Write a 1 to the status bits that must be cleared.

For the Tier 2 status register bits, Bits[31:29],

1. Read the status register to see which Tier 2 register is set.

2. Read the Tier 2 register (CHIP_STATUS, EVENT_STATUS,

or MS_STATUS_IRQ); the register is cleared on a read.

CF2/ZX/DREADY EVENT PIN

The CF2 pin is multiplexed with the ZX and DREADY functions

that track the state of zero crossings and when new data is

available, respectively. The ZX pin functionality goes high with

negative to positive zero crossings and goes low with positive

negative zero crossings. The DREADY pin functionality outputs

a 1 ms pulse when new data is ready.

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