Datasheet

Data Sheet ADE9153A
Rev. 0 | Page 25 of 50
Reset Energy Register on Read
The user can reset the energy register on a read using the
RD_RST_EN bit in the EP_CFG register. In this way, the
value in the user energy register is reset when it is read.
Power Accumulation
The ADE9153A accumulates the total active, fundamental
reactive, and total apparent powers into the AWATT_ACC,
AFVAR_ACC, and AVA_ACC 32-bit signed registers, respectively.
This accumulation can be used as an averaged power reading.
The number of samples accumulated is set using the PWR_
TIME register. The PWRRDY bit in the status register is set
after PWR_TIME + 1 samples accumulate at 4 kSPS. The
maximum value of the PWR_TIME register is 8191 decimal,
and the maximum power accumulation time is 1.024 sec.
The CFx SIGN, AVARSIGN, and AWSIGN bits in t he
PHSIGN register indicate the sign of accumulated powers over
the PWR_TIME interval. When the sign of the accumulated
power changes, the corresponding REVx bits in the status register
are set and
IRQ
generates an interrupt.
The ADE9153A allows the user to accumulate total active
power and fundamental reactive power into separate positive
and negative accumulation registers: PWATT_ACC, NWATT_
ACC, PFVAR_ACC, and NFVAR_ACC. A new accumulation
from zero begins when the power update interval set in
PWR_TIME elapses.
No Load Detection Feature
The ADE9153A features no load detection for each energy to
prevent energy accumulation due to noise. If the accumulated
energy over the user defined time period is below the user defined
threshold, zero energy is accumulated into the energy register.
The NOLOAD_TMR bits in the EP_CFG register determine the
no load time period, and the ACT_NL_LVL, REACT_NL_LVL,
and APP_NL_LVL registers contain the user defined no load
threshold. The no load status is available in the PHNOLOAD
register and the status register, which can be driven to the
IRQ
interrupt pin.
AWATT
AVA
AFVAR
CFxSEL
100
000
010
CFxSEL
WTHR
CFx_LT
CF_LTMR
CFxDIS
4.096MHz
DIGITAL
TO
FREQUENCY
512
CFxDEN
CF_ACC_CLR
0
1
1
CFx PIN
PULSE
WIDTH
CONFIGURATION
ADE9153A
CFx BITS
VATHR
VARTHR
100
000
010
16258-150
Figure 50. Digital to Frequency Conversion for CFx
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