Datasheet

Data Sheet ADE7953
Rev. B | Page 9 of 72
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
09320-004
1ZX
2RESET
3VINTD
4
DGND
5IAP
6IAN
7PULL_HIGH
17 VDD
18 CLKIN
19 CLKOUT
20 REVP
21 ZX_I
16 AGND
15 VINTA
8
PULL_HIGH
9
IBP
10
IBN
1
1
VN
12
VP
13
REF
14
PULL_LOW
24
CF2
25
SCLK
26
MISO/SDA/Tx
27
MOSI/SCL/Rx
28
CS
23
CF1
22
IRQ
ADE7953
TOP VIEW
(Not to Scale)
NOTES
1. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPOSED
PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB
TO CONFER MECHANICAL STRENGTH TO THE PACKAGE.
CONNECT THE PAD TO AGND AND DGND.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 ZX Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel Zero Crossing section. This pin can
be configured to output a range of alternative power quality signals (see the Alternative Output Functions
section).
2
RESET
Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for at minimum of 10 µs.
3 VINTD This pin provides access to the 2.5 V digital LDO. This pin should be decoupled with a 4.7 µF capacitor in
parallel with a 100 nF ceramic capacitor.
4 DGND Ground Reference for the Digital Circuitry.
5, 6 IAP, IAN Analog Input for Current Channel A (Phase Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The maximum pin voltage for single-ended use is ±250 mV. The PGA associated
with this input has a maximum gain stage of 22 (see the Analog Inputs section).
7, 8 PULL_HIGH These pins should be connected to VDD for proper operation.
9, 10 IBP, IBN Analog Input for Current Channel B (Neutral Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog
Inputs section).
11, 12 VN, VP Analog Input for Voltage Channel. This differential voltage input has a maximum input range of ±500 mV. The
PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section).
13
REF
This pin provides access to the on-chip voltage reference. The internal reference has a nominal voltage
of 1.2 V. This pin should be decoupled with a 4.7 µF capacitor in parallel with a 100 nF ceramic capacitor.
Alternatively, an external reference voltage of 1.2 V can be applied to this pin (see the
Reference Circuit
section).
14 PULL_LOW This pin should be connected to AGND for proper operation.
15 VINTA This pin provides access to the 2.5 V analog LDO. This pin should be decoupled with a 4.7 µF capacitor in
parallel with a 100 nF ceramic capacitor.
16 AGND Ground Reference for the Analog Circuitry.
17 VDD Power Supply (3.3 V) for the ADE7953. For specified operation, the input to this pin should be within
3.3 V ± 10%. This pin should be decoupled with a 10 µF capacitor in parallel with a 100 nF ceramic capacitor.
18 CLKIN Master Clock Input for the ADE7953. An external clock can be provided at this input. Alternatively, a parallel
resonant AT crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the
ADE7953
. The clock frequency for specified operation is 3.58 MHz. Ceramic load capacitors of a few tens of
picofarads
should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for
the load capacitance requirements.
19 CLKOUT A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7953.