Datasheet

Data Sheet ADE7953
Rev. B | Page 7 of 72
I
2
C Interface Timing
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T
MIN
to T
MAX
= −40°C to +85°C, unless otherwise noted.
Table 3.
Standard Mode Fast Mode
Parameter Description Min
1
Max
1
Min
1
Max
1
Unit
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
HD;STA
Hold time for a start or repeated start condition 4.0 0.6 μs
t
LOW
Low period of SCL clock 4.7 1.3 μs
t
HIGH
High period of SCL clock 4.0 0.6 μs
t
SU;STA
Setup time for a repeated start condition 4.7 0.6 μs
t
HD;DAT
Data hold time 0.1 3.45 0.1 0.9 μs
t
SU;DAT
Data setup time 250 100 ns
t
R
Rise time of SDA and SCL signals 1000 20 300 ns
t
F
Fall time of SDA and SCL signals 300 20 300 ns
t
SU;STO
Setup time for stop condition 4.0 0.6 μs
t
BUF
Bus-free time between a stop and start condition 4.7 1.3 μs
t
SP
Pulse width of suppressed spikes N/A 50 ns
1
Min and max values are typical minimum and maximum values.
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C Interface Timing Diagram
t
F
t
R
t
HD;DAT
t
HD;STA
t
HIGH
t
SU;STA
t
SU;DAT
t
F
t
HD;STA
t
SP
t
SU;STO
t
R
t
BUF
t
LOW
SDA
SCL
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
09320-002
Figure 3. I
2
C Interface Timing