Datasheet

ADE7953 Data Sheet
Rev. B | Page 68 of 72
LAYOUT GUIDELINES
Figure 78 presents a basic schematic of the ADE7953 together
with its surrounding circuitry, decoupling capacitors at pins
VDD, VINTA, VINTD, and REF, and the 3.58 MHz crystal and
its load capacitors. The rest of the pins are dependent on the
particular application and are not shown here.
Figure 77 presents a proposed layout of a printed circuit board
(PCB) with two layers that have the components placed only on
the top of the board. Following these layout guidelines will help
in creating a low noise design with higher immunity to EMC
influences.
The VDD, VINTA, VINTD, and REF pins each have two
decoupling capacitors, one of μF
order and a ceramic one of
220 nF or 100 nF. These ceramic capacitors need to be placed
closest to the ADE7953 as they decouple high frequency noises,
while the μF ones need to be place in close proximity.
The exposed pad of the ADE7953 is soldered to an equivalent
pad on the PCB. The AGND, DGND, and PULL_LOW pins
traces of the ADE7953 are then routed directly in to the PCB
pad.
The bottom layer is composed mainly of a ground plane
surrounding as much as possible the through hole crystal pins.
09320-178
Figure 77. ADE7953 Top Layer Printed Circuit Board
09320-177
ADE7953
U1
4
DGND
16
AGND PAD
14
PULL_LOW
7
PULL_HIGH
8
PULL_HIGH
IAP
5
IAN
6
IBP
9
IBN
10
VN
11
VP
12
CLKIN
18
SCLK
25
MOSI/SCL/Rx
27
CS 28
REF
13
1
ZX
15
VINTA
19
CLKOUT
22
IRQ
21
ZX_I
20
REVP
23
CF1
24
CF2
26
MISO/SDA/Tx
RESET
2
C8
20pF
C7
20pF
17
VDD
C6
0.1µF
C5
10µF
3
VINTD
C4
4.7µF
C3
0.1µF
C10
4.7µF
C9
0.1µF
C2
4.7µF
C1
0.1µF
Y1
3.58MHz
12
Figure 78. ADE7953 Crystal and Capacitors Connections