Datasheet

ADE7953 Data Sheet
Rev. B | Page 60 of 72
ADE7953 REGISTERS
The ADE7953 contains registers that are 8, 16, 24, and 32 bits long. All signed registers are in the twos complement format with the
exception of the PHCALA and PHCALB registers, which are in sign magnitude format. The 24-bit and 32-bit registers contain the same
data but can be accessed in two different register lengths. The 24-bit register option increases communication speed; the 32-bit register
option provides simplicity when coding with the long format. When accessing the 32-bit registers, only the lower 24 bits contain valid
data (the upper 8 bits are sign extended). A write to a 24-bit register changes the value in the corresponding 32-bit register, and vice versa.
Therefore, each 24-bit/32-bit register can be thought of as one memory location that can be accessed via two different paths.
Table 13. 8-Bit Registers
Address Register Name R/W Default Type Register Description
0x000 SAGCYC R/W 0x00 Unsigned Sag line cycles
0x001 DISNOLOAD R/W 0x00 Unsigned No-load detection disable (see Table 16)
0x004 LCYCMODE R/W 0x40 Unsigned Line cycle accumulation mode configuration (see Table 17)
0x007 PGA_V R/W 0x00 Unsigned Voltage channel gain configuration (Bits[2:0])
0x008 PGA_IA R/W 0x00 Unsigned Current Channel A gain configuration (Bits[2:0])
0x009 PGA_IB R/W 0x00 Unsigned Current Channel B gain configuration (Bits[2:0])
0x040 WRITE_PROTECT R/W 0x00 Unsigned Write protection bits (Bits[2:0])
0x0FD LAST_OP R 0x00 Unsigned
Contains the type (read or write) of the last successful communication (0x35 =
read; 0xCA = write)
0x0FF LAST_RWDATA R 0x00 Unsigned Contains the data from the last successful 8-bit register communication
0x702 Version R N/A Unsigned Contains the silicon version number
0x800 EX_REF R/W 0x00 Unsigned Reference input configuration: set to 0 for internal; set to 1 for external
Table 14. 16-Bit Registers
Address Register Name R/W Default Type Register Description
0x100 ZXTOUT R/W 0xFFFF Unsigned Zero-crossing timeout
0x101 LINECYC R/W 0x0000 Unsigned Number of half line cycles for line cycle energy accumulation mode
0x102 CONFIG R/W 0x8004 Unsigned Configuration register (see Table 18)
0x103 CF1DEN R/W 0x003F Unsigned
CF1 frequency divider denominator. When modifying this register, two
sequential write operations must be performed to ensure that the write is
successful.
0x104 CF2DEN R/W 0x003F Unsigned
CF2 frequency divider denominator. When modifying this register, two
sequential write operations must be performed to ensure that the write is
successful.
0x107 CFMODE R/W 0x0300 Unsigned CF output selection (see Table 19)
0x108 PHCALA R/W 0x0000 Signed
Phase calibration register (Current Channel A). This register is in sign
magnitude format.
0x109 PHCALB R/W 0x0000 Signed
Phase calibration register (Current Channel B). This register is in sign
magnitude format.
0x10A PFA R 0x0000 Signed Power factor (Current Channel A)
0x10B PFB R 0x0000 Signed Power factor (Current Channel B)
0x10C ANGLE_A R 0x0000 Signed Angle between the voltage input and the Current Channel A input
0x10D ANGLE_B R 0x0000 Signed Angle between the voltage input and the Current Channel B input
0x10E Period R 0x0000 Unsigned Period register
0x110 ALT_OUTPUT R/W 0x0000 Unsigned Alternative output functions (see Table 20)
0x1FE LAST_ADD R 0x0000 Unsigned Contains the address of the last successful communication
0x1FF LAST_RWDATA R 0x0000 Unsigned Contains the data from the last successful 16-bit register communication
0x120 Reserved R/W 0x0000 Unsigned
This register should be set to 30h to meet the performance specified in
Table 1. To modify this register, it must be unlocked by setting Register
Address 0xFE to 0xAD immediately prior.