Datasheet

ADE7953 Data Sheet
Rev. B | Page 6 of 72
TIMING CHARACTERISTICS
SPI Interface Timing
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T
MIN
to T
MAX
= −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Description Min
1
Max
1
Unit
t
CS
CS to SCLK edge 50 ns
t
SCLK
SCLK period 200 ns
t
SL
SCLK low pulse width 80 ns
t
SH
SCLK high pulse width 80 ns
t
DAV
Data output valid after SCLK edge 80 ns
t
DSU
Data input setup time before SCLK edge 70 ns
t
DHD
Data input hold time after SCLK edge 5 ns
t
DF
Data output fall time 20 ns
t
DR
Data output rise time 20 ns
t
SR
SCLK rise time 20 ns
t
SF
SCLK fall time 20 ns
t
DIS
MISO disabled after CS rising edge 5 40 ns
t
SFS
CS high after SCLK edge 0 ns
t
SFS_LK
CS high after SCLK edge (when writing to
COMM_LOCK bit)
1200 ns
1
Min and max values are typical minimum and maximum values.
SPI Interface Timing Diagram
LSB IN
INTERMEDIATE BITS
INTERMEDIATE BITS
t
SFS_LK
t
SFS
t
DIS
t
CS
t
SL
t
DF
t
SH
t
DHD
t
DAV
t
DSU
t
SR
t
SF
t
DR
t
SCLK
MSB IN
MOSI
MISO
SCLK
CS
09320-003
MSB OUT LSB OUT
Figure 2. SPI Interface Timing