Datasheet

ADE7953 Data Sheet
Rev. B | Page 54 of 72
I
2
C Read Operations
The I
2
C read operation is performed in two stages. The first
stage sets the pointer to the address of the register to be
accessed. The second stage reads the contents of the register.
As shown in Figure 71, the first stage is initiated when the
master issues a start condition, which consists of the slave
address and the read/write bit. Because this first step sets up
the pointer to the address, the LSB of the start byte should be
set to 0 (write). The start condition is followed by the 16-bit
address of the target register. After each byte is received, the
ADE7953 issues an acknowledge (ACK) to the master.
The second stage of the read operation begins with the master
generating a new start condition. This start condition consists of
the same slave address but with the LSB set to 1 to signify that a
read is being issued. After this byte is received, the ADE7953
issues an acknowledge (ACK). The ADE7953 then sends the
register contents to the master, which acknowledges the reception
of each byte. All bytes are sent MSB first. The register contents
can be 8, 16, 24, or 32 bits long. After the final byte of register
data is received, the master issues a stop condition in place of
the acknowledge to indicate the completion of the communication.
The I
2
C read operation is shown in Figure 71.
ACK GENERATED BY
ADE7953
ACK GENERATED BY
MASTER
STAR
T
S
A
C
K
A
C
K
A
C
K
0
15
SLAVE ADDRESS
MSB OF REGISTERADDRESS
LSB OF REGISTERADDRESS
87 0
1110000
START
STOP
S
A
C
K
A
C
K
A
C
K
A
C
K
P0
SLAVE ADDRESS
BYTE 3 (MSB)
OF REGISTER
BYTE 2 OF REGISTER
BYTE 1 OF REGISTER
BYTE 0 (LSB)
OF REGISTER
23 16 15 8
7
0
07
1110001
ACK GENERATED BY
ADE7953
09320-060
READ/WRITE
READ/WRITE
Figure 71. I
2
C Read