Datasheet

ADE7953 Data Sheet
Rev. B | Page 44 of 72
A zero-crossing event on any of the three input channels can be
configured to trigger an external interrupt. All zero-crossing
external interrupts are disabled by default. The voltage channel
zero-crossing interrupt is enabled by setting the ZXV bit (Bit 15)
in the IRQENA register (Address 0x22C and Address 0x32C). If
this bit is set, a voltage channel zero-crossing event causes the
IRQ
pin to go low. The Current Channel A zero-crossing interrupt is
enabled by setting the ZXIA bit (Bit 12) in the IRQENA register
(Address 0x22C and Address 0x32C). If this bit is set, a Current
Channel A zero-crossing event causes the
IRQ
pin to go low. The
Current Channel B zero-crossing interrupt is enabled by setting
the ZXIB bit (Bit 12) in the IRQENB register (Address 0x22F
and Address 0x32F). If this bit is set, a Current Channel B zero-
crossing event causes the
IRQ
pin to go low (see the ADE7953
Interrupts section).
ZERO-CROSSING TIMEOUT
The ADE7953 includes a zero-crossing timeout feature that is
designed to detect when no zero crossings are obtained over a
programmable time period. This feature is available on both
current channels and the voltage channel and can be used to
detect when the input signal has dropped out. The duration of
the zero-crossing timeout is programmed in the 16-bit ZXTOUT
register (Address 0x100). The same timeout duration is used for
all three channels. The value in the ZXTOUT register is decre-
mented by 1 LSB every 14 kHz (CLKIN/256). If a zero crossing
is obtained, the ZXTOUT register is reloaded. If the ZXTOUT
register reaches 0, a zero-crossing timeout event is issued. The
ZXTOUT register has a resolution of 0.07 ms (1/14 kHz); there-
fore, the maximum programmable timeout period is 4.58 seconds.
As shown in Figure 64, a zero-crossing event causes one of the
zero-crossing timeout bits—ZXTO, ZXTO_IA, or ZXTO_IB—
to be set to 1. The ZXTO and ZXTO_IA bits are located in the
IRQSTATA register (Address 0x22D and Address 0x32D) and
are set when a zero-crossing timeout event occurs on the voltage
channel or on Current Channel A, respectively. The ZXTO_IB
bit is located in the IRQSTATB register (Address 0x230 and
Address 0x330) and is set when a zero-crossing timeout event
occurs on Current Channel B.
ZXTOUT
ADDRESS 0x100
INPUT
SIGNAL
ZXTO_x
09320-033
Figure 64. Zero-Crossing Timeout
Three interrupts are associated with the zero-crossing timeout
feature. If enabled, a zero-crossing timeout event causes the
external
IRQ
pin to go low. The interrupt associated with the
voltage channel zero-crossing timeout can be enabled by setting
the ZXTO bit (Bit 14) of the IRQENA register (Address 0x22C
and Address 0x32C). The Current Channel A interrupt can be
enabled by setting the ZXTO_IA bit (Bit 11) of the IRQENA
register (Address 0x22C and Address 0x32C), and the Current
Channel B interrupt can be enabled by setting the ZXTO_IB bit
(Bit 11) of the IRQENB register (Address 0x22F and Address
0x32F). All three interrupts are disabled by default (see the
ADE7953 Interrupts section).
ZERO-CROSSING THRESHOLD
To prevent spurious zero crossings when a very small input is
present, an internal threshold is included on all channels of the
ADE7953. This fixed threshold is set to a range of 1250:1 of the
input full scale. If any input signal falls below this level, no zero-
crossing signals are produced by the ADE7953 because they can
be assumed to be noise. This threshold affects both the external
zero-crossing pins, ZX (Pin 1) and ZX_I (Pin 21), as well as the
zero-crossing interrupt function. At inputs of lower than 1250:1
of the full scale, the zero-crossing timeout signal continues to
function and issues an event according to the time duration
programmed in the ZXTOUT register (Address 0x100).