Datasheet

ADE7880 Data Sheet
Rev. A| Page 94 of 104
Bit Mnemonic Default Value Description
20 MISMTCH 0
When this bit is set to 1, it enables an interrupt
when
ISUMLVLINWVISUM >−
is greater than the value indicated in
ISUMLVL register.
22:21 Reserved 00 Reserved. These bits do not manage any functionality.
23 PKI 0
When this bit is set to 1, it enables an interrupt when the period used to detect the
peak value in the current channel has ended.
24 PKV 0
When this bit is set to 1, it enables an interrupt when the period used to detect the
peak value in the voltage channel has ended.
25 CRC 0
When this bit is set to 1, it enables an interrupt when the latest checksum value is
different from the checksum value computed when Run register was set to 1.
31:26 Reserved 000 0000 Reserved. These bits do not manage any functionality.
Table 40. PHSTATUS Register (Address 0xE600)
Bit Mnemonic Default Value Description
2:0 Reserved 000 Reserved. These bits are always 0.
3 OIPHASE[0] 0 When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.
4 OIPHASE[1] 0 When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.
5 OIPHASE[2] 0 When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.
8:6 Reserved 000 Reserved. These bits are always 0.
9 OVPHASE[0] 0 When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
10 OVPHASE[1] 0 When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
11 OVPHASE[2] 0 When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
12 VSPHASE[0] 0 0: Phase A voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase A voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase A voltage generates Bit 16
(SAG) in the STATUS1 register.
13 VSPHASE[1] 0 0: Phase B voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase B voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase B voltage generates Bit 16
(SAG) in the STATUS1 register.
14 VSPHASE[2] 0 0: Phase C voltage is above SAGLVL level for SAGCYC half line cycles
1: Phase C voltage is below SAGLVL level for SAGCYC half line cycles
When this bit is switches from 0 to 1 or from 1 to 0, the Phase C voltage generates Bit 16
(SAG) in the STATUS1 register.
15 Reserved 0 Reserved. This bit is always 0.
Table 41. PHNOLOAD Register (Address 0xE608)
Bit Mnemonic Default Value Description
0 NLPHASE[0] 0
0: Phase A is out of no load condition determined by the Phase A total active power and
apparent power.
1: Phase A is in no load condition determined by phase A total active power and apparent
power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
1 NLPHASE[1] 0
0: Phase B is out of no load condition determined by the Phase B total active power and
apparent power.
1: Phase B is in no load condition determined by the Phase B total active power and
apparent power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
2 NLPHASE[2] 0
0: Phase C is out of no load condition determined by the Phase C total active power and
apparent power.
1: Phase C is in no load condition determined by the Phase C total active power and
apparent power. Bit set together with Bit 0 (NLOAD) in the STATUS1 register.
3 FNLPHASE[0] 0 0: Phase A is out of no load condition based on fundamental active/reactive powers.
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.