Datasheet

ADE7880 Data Sheet
Rev. A | Page 84 of 104
Address
Register
Name R/W
1
Bit
Length
Bit Length During
Communication
2
Type
3
Default Value Description
0x43B0 HZWATTOS R/W 24 32 ZPSE S 0x000000 Active power offset adjust on harmonic Z
(see
Harmonics Calculations section for details).
0x43B1 HXVAROS R/W 24 32 ZPSE S 0x000000 Aactive power offset adjust on harmonic X
(see
Harmonics Calculations section for details).
0x43B2 HYVAROS R/W 24 32 ZPSE S 0x000000 Active power offset adjust on harmonic Y
(see
Harmonics Calculations section for details).
0x43B3 HZVAROS R/W 24 32 ZPSE S 0x000000 Aactive power offset adjust on harmonic Z
(see
Harmonics Calculations section for details).
0x43B4 HXIRMSOS R/W 24 32 ZPSE S 0x000000 Current rms offset on harmonic X
(see
Harmonics Calculations section for details).
0x43B5 HYIRMSOS R/W 24 32 ZPSE S 0x000000 Current rms offset on harmonic Y
(see
Harmonics Calculations section for details).
0x43B6 HZIRMSOS R/W 24 32 ZPSE S 0x000000 Current rms offset on harmonic Z
(see
Harmonics Calculations section for details).
0x43B7 HXVRMSOS R/W 24 32 ZPSE S 0x000000 Voltage rms offset on harmonic X
(see
Harmonics Calculations section for details).
0x43B8 HYVRMSOS R/W 24 32 ZPSE S 0x000000 Voltage rms offset on harmonic Y
(see
Harmonics Calculations section for details).
0x43B9 HZVRMSOS R/W 24 32 ZPSE S 0x000000 Voltage rms offset on harmonic Z
(see
Harmonics Calculations section for details).
0x43BA
to
0x43BF
Reserved N/A N/A N/A N/A 0x000000 These memory locations should not be written for
proper operation.
0x43C0 AIRMS R 24 32 ZP S N/A Phase A current rms value.
0x43C1 AVRMS R 24 32 ZP S N/A Phase A voltage rms value.
0x43C2 BIRMS R 24 32 ZP S N/A Phase B current rms value.
0x43C3 BVRMS R 24 32 ZP S N/A Phase B voltage rms value.
0x43C4 CIRMS R 24 32 ZP S N/A Phase C current rms value.
0x43C5 CVRMS R 24 32 ZP S N/A Phase C voltage rms value.
0x43C6 NIRMS R 24 32 ZP S N/A Neutral current rms value.
0x43C7 ISUM R 24 32 ZP S N/A Sum of IAWV, IBWV and ICWV registers.
0x43C8
to
0x43FF
Reserved N/A N/A N/A N/A N/A These memory locations should not be written for
proper operation.
1
R is read, and W is write.
2
32 ZPSE = 24-bit signed register that is transmitted as a 32-bit word with four MSBs padded with 0s and sign extended to 28 bits. Whereas 32 ZP = 28- bit or 24-bit
signed or unsigned register that is transmitted as a 32-bit word with four or eight MSBs, respectively, padded with 0s.
3
U is unsigned register, and S is signed register in twos complement format.
Table 31. Internal DSP Memory RAM Registers
Address
Register
Name R/W
1
Bit
Length
Bit Length
During
Communication Type
2
Default
Value Description
0xE203 Reserved R/W 16 16 U 0x0000
This memory location should not be written for
proper operation.
0xE228 Run R/W 16 16 U 0x0000
Run register starts and stops the DSP. See the
Digital Signal Processor section for more details.
1
R is read, and W is write.
2
U is unsigned register, and S is signed register in twos complement format.